Texas Instruments TMS320DM646x Manuel utilisateur

TMS320DM646x DMSoCDDR2 Memory Controller

User's Guide

Literature Number: SPRUEQ4C

February 2009

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Contents
Preface ........................................................................................................................................ 61 Introduction ......................................................................................................................... 71.1 Purpose of the Peripheral ................................................................................................ 71.2 Features .................................................................................................................... 71.3 Functional Block Diagram ................................................................................................ 71.4 Supported Use Case Statement ........................................................................................ 81.5 Industry Standard(s) Compliance Statement .......................................................................... 82 Architecture ........................................................................................................................ 82.1 Clock Control .............................................................................................................. 82.2 Memory Map ............................................................................................................. 102.3 Signal Descriptions ...................................................................................................... 102.4 Protocol Description(s) .................................................................................................. 112.5 Memory Width and Byte Alignment ................................................................................... 192.6 Address Mapping ........................................................................................................ 202.7 DDR2 Memory Controller Interface ................................................................................... 232.8 Refresh Scheduling ..................................................................................................... 262.9 Self-Refresh Mode....................................................................................................... 262.10 Reset Considerations ................................................................................................... 272.11 VTP IO Buffer Calibration .............................................................................................. 282.12 Auto-Initialization Sequence ............................................................................................ 282.13 Interrupt Support ......................................................................................................... 302.14 DMA Event Support ..................................................................................................... 312.15 Power Management ..................................................................................................... 312.16 Emulation Considerations .............................................................................................. 323 Use Cases ......................................................................................................................... 333.1 Connecting the DDR2 Memory Controller to DDR2 Memory ...................................................... 333.2 Configuring Memory-Mapped Registers to Meet DDR2-667 Specification ...................................... 334 Registers ........................................................................................................................... 394.1 SDRAM Status Register (SDRSTAT) ................................................................................. 394.2 SDRAM Bank Configuration Register (SDBCR) ..................................................................... 404.3 SDRAM Refresh Control Register (SDRCR)......................................................................... 424.4 SDRAM Timing Register (SDTIMR) ................................................................................... 434.5 SDRAM Timing Register 2 (SDTIMR2) ............................................................................... 444.6 Peripheral Bus Burst Priority Register (PBBPR) .................................................................... 454.7 Interrupt Raw Register (IRR) ........................................................................................... 464.8 Interrupt Masked Register (IMR) ...................................................................................... 474.9 Interrupt Mask Set Register (IMSR) ................................................................................... 484.10 Interrupt Mask Clear Register (IMCR) ................................................................................ 494.11 DDR PHY Control Register (DDRPHYCR) ........................................................................... 504.12 DDR VTP IO Control Register (VTPIOCR) ........................................................................... 51Appendix A Revision History ...................................................................................................... 52
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List of Figures
1 Data Paths to DDR2 Memory Controller .................................................................................. 82 DDR2 Memory Controller Clock Block Diagram ......................................................................... 93 DDR2 Memory Controller Signals ........................................................................................ 104 Refresh Command ......................................................................................................... 135 DCAB Command ........................................................................................................... 146 DEAC Command ........................................................................................................... 157 ACTV Command ........................................................................................................... 168 DDR2 READ Command ................................................................................................... 179 DDR2 WRT Command .................................................................................................... 1810 DDR2 MRS and EMRS Command ...................................................................................... 1911 Byte Alignment .............................................................................................................. 2012 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 2213 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 2314 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 2415 DDR2 Memory Controller Reset Block Diagram ....................................................................... 2716 DDR2 Memory Controller Power and Sleep Controller Diagram .................................................... 3117 Connecting DDR2 Memory Controller for 32-Bit Connection ......................................................... 3418 Connecting DDR2 Memory Controller for 16-Bit Connection ......................................................... 3519 SDRAM Status Register (SDRSTAT).................................................................................... 3920 SDRAM Bank Configuration Register (SDBCR) ....................................................................... 4021 SDRAM Refresh Control Register (SDRCR) ........................................................................... 4222 SDRAM Timing Register (SDTIMR) ..................................................................................... 4323 SDRAM Timing Register 2 (SDTIMR2).................................................................................. 4424 Peripheral Bus Burst Priority Register (PBBPR) ....................................................................... 4525 Interrupt Raw Register (IRR) ............................................................................................. 4626 Interrupt Masked Register (IMR) ......................................................................................... 4727 Interrupt Mask Set Register (IMSR) ..................................................................................... 4828 Interrupt Mask Clear Register (IMCR) ................................................................................... 4929 DDR PHY Control Register (DDRPHYCR) ............................................................................. 5030 DDR VTP IO Control Register (VTPIOCR) ............................................................................. 51
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List of Tables
1 PLLC2 Configuration ........................................................................................................ 92 DDR2 Memory Controller Signal Descriptions ......................................................................... 113 DDR2 SDRAM Commands ............................................................................................... 114 Truth Table for DDR2 SDRAM Commands ............................................................................ 125 Addressable Memory Ranges ............................................................................................ 196 Bank Configuration Register Fields for Address Mapping ............................................................ 207 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 218 Logical Address-to-DDR2 SDRAM Address Map for 16-Bit SDRAM ............................................... 219 DDR2 Memory Controller FIFO Description ............................................................................ 2310 Refresh Urgency Levels ................................................................................................... 2611 Reset Sources .............................................................................................................. 2712 DDR2 SDRAM Configuration by MRS Command ..................................................................... 2913 DDR2 SDRAM Configuration by EMRS(1) Command ................................................................ 2914 SDBCR Configuration ..................................................................................................... 3315 DDR2 Memory Refresh Specification ................................................................................... 3616 SDRCR Configuration ..................................................................................................... 3617 SDTIMR Configuration ..................................................................................................... 3718 SDTIMR2 Configuration ................................................................................................... 3719 DDRPHYCR Configuration ................................................................................................ 3820 DDR2 Memory Controller Registers ..................................................................................... 3921 SDRAM Status Register (SDRSTAT) Field Descriptions ............................................................. 3922 SDRAM Bank Configuration Register (SDBCR) Field Descriptions ................................................. 4023 SDRAM Refresh Control Register (SDRCR) Field Descriptions ..................................................... 4224 SDRAM Timing Register (SDTIMR) Field Descriptions ............................................................... 4325 SDRAM Timing Register 2 (SDTIMR2) Field Descriptions ........................................................... 4426 Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions ................................................. 4527 Interrupt Raw Register (IRR) Field Descriptions ....................................................................... 4628 Interrupt Masked Register (IMR) Field Descriptions ................................................................... 4729 Interrupt Mask Set Register (IMSR) Field Descriptions ............................................................... 4830 Interrupt Mask Clear Register (IMCR) Field Descriptions ............................................................. 4931 DDR PHY Control Register (DDRPHYCR) Field Descriptions ....................................................... 5032 DDR VTP IO Control Register (VTPIOCR) Field Descriptions ....................................................... 51A-1 Document Revision History ............................................................................................... 52
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PrefaceSPRUEQ4C – February 2009

Read This First

About This Manual

This document describes the DDR2 memory controller in the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.

SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

SPRU871 —TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

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1 Introduction

1.1 Purpose of the Peripheral

1.2 Features

1.3 Functional Block Diagram

User's GuideSPRUEQ4C – February 2009

DDR2 Memory Controller

This document describes the DDR2 memory controller in the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).

The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices. Memories types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memoriesare not supported. The DDR2 memory controller is the major memory location for program and datastorage.

The DDR2 memory controller supports the following features:•JESD79D-2A standard compliant DDR2 SDRAM•256 MBbyte memory space•Data bus width of 32 or 16 bits•CAS latencies: 2, 3, 4, and 5•Internal banks: 1, 2, 4, and 8•Burst length: 8•Burst type: sequential•1 CS signal•Page sizes: 256, 512, 1024, and 2048•SDRAM autoinitialization

•Self-refresh mode•Prioritized refresh•Programmable refresh rate and backlog counter•Programmable timing parameters•Little endian

The DDR2 memory controller is the main interface to external DDR2 memory. Figure 1 displays thegeneral data paths to on-chip peripherals and external DDR2 SDRAM.

Master peripherals, EDMA, the ARM processor, and DSP can access the DDR2 memory controllerthrough the switched central resource (SCR).

SPRUEQ4C – February 2009 DDR2 Memory Controller 7Submit Documentation Feedback

SCR DDR2

memory

controller

BUS BUS External

DDR2 SDRAM

ARM

DSP

Master

peripherals

EDMA

VPSS

1.4 Supported Use Case Statement

1.5 Industry Standard(s) Compliance Statement

2 Architecture

2.1 Clock Control

2.1.1 Clock Source

Architecture

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Figure 1. Data Paths to DDR2 Memory Controller

The DDR2 memory controller supports JESD79D-2A DDR2-667 SDRAM memories utilizing either 32-bitor 16-bit of the DDR2 memory controller data bus. See Section 3 for more details.

•The DDR2 memory controller does not support the On Die Termination (ODT) function.•The DDR2 memory controller supports differential DQS signals.

This section describes the architecture of the DDR2 memory controller as well as how it is structured andhow it works within the context of the system-on-a-chip. The DDR2 memory controller can gluelesslyinterface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode andprioritized refresh. In addition, it provides flexibility through programmable parameters such as the refreshrate, CAS latency, and many SDRAM timing parameters. The following sections include details on how tointerface and properly configure the DDR2 memory controller to perform read and write operations toexternally-connected DDR2 SDRAM devices. Also, Section 3 provides a detailed example of interfacingthe DDR2 memory controller to a common DDR2 SDRAM device.

The DDR2 memory controller receives two input clocks from internal clock sources, SYSCLK2 andPLL2_SYSCLK1 (Figure 2 ). SYSCLK2 is a divided-down version of the DSP clock. PLL2_SYSCLK1should be configured to clock at the frequency of the desired data rate, or stated similarly, it shouldoperate at twice the frequency of the desired DDR2 memory clock. DDR_CLK and DDR_CLK are the twooutput clocks of the DDR2 memory controller providing the interface clock to the DDR2 SDRAM memory.These two clocks operate at a frequency of PLL2_SYSCLK1/2.

SYSCLK2 and PLL2_SYSCLK1 are sourced from two independent PLLs (Figure 2 ). SYSCLK2 is sourcedfrom PLL controller 1 (PLLC1) and PLL2_SYSCLK1 is sourced from PLL controller 2 (PLLC2).

SYSCLK2 is clocked at a fixed divider ratio of 2 in PLL1, meaning SYSCLK2 is clocked at a frequency ofPLL1/2. Once inside the DDR2 memory controller, this signal is called VCLK.

PLLC2 has a programmable divider that is used to divide-down the output clock of PLL2. This dividershould be configured such that PLLC2 supplies the PLL2_SYSCLK1 at the desired frequency. Forexample, if a 310.5-MHZ DDR2 interface clock (DDR_CLK) is desired, then PLLC2 must be configured togenerate a 621-MHZ clock on PLL2_SYSCLK1. Once inside the DDR2 memory controller,PLL2_SYSCLK1 is called X2_CLK.

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DDR2

memory

controller

PLLC2

PLLC1

X2_CLK

VCLK

DDR_CLK DDR_CLK

PLL2_SYSCLK1

PLL1_SYSCLK2

2.1.2 Clock Configuration

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Architecture

Figure 2. DDR2 Memory Controller Clock Block Diagram

The frequency of PLL2_SYSCLK1 is configured by selecting the appropriate PLL multiplier and dividerratio. The PLL multiplier and divider ratio are selected by programming registers within PLLC2. Table 1shows a list of PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data inTable 1 is derived by assuming a 27-MHZ reference clock. See the TMS320DM646x DMSoC ARMSubsystem Reference Guide (SPRUEP9 ) for information on the PLL controller.

Note: PLLC2 should be configured and a stable clock present on PLL2_SYSCLK1 before releasingthe DDR2 memory controller from reset.

Table 1. PLLC2 Configuration

PLL PLL PLL2_SYSCLK1 DDR2 ClockMultiplier Frequency (MHZ) Divider Ratio Frequency (MHZ) Frequency (MHZ)

13 351 1 351 175.514 378 1 378 18915 405 1 405 202.516 432 1 432 21617 459 1 459 229.518 486 1 486 24319 513 1 513 256.520 540 1 540 27021 567 1 567 283.522 594 1 594 29723

(1)

621 1 621 310.5(1)

Applies only to 729 MHZ devices.

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2.1.3 DR2 Memory Controller Internal Clock Domains

2.2 Memory Map

2.3 Signal Descriptions

DDR_D[31:0]

DDR2

memory

controller

DDR_CLK

DDR_CS

DDR_CKE

DDR_RAS

DDR_WE

DDR_BA[2:0]

DDR_CAS

DDR_DQGATE[3:0]

DDR_DQS[3:0]

DDR_ZN

DDR_ZP

50 Ω

DDR_A[14:0]

DDR_DQS[3:0]

DDR_DQM[3:0]

DDR_ODT0

DDR_VREF

Architecture

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There are two clock domains within the DDR2 memory controller. The two clock domains are driven byVCLK and a divided-down by 2 version of PLL2_SYSCLK1 called MCLK. The command FIFO, write FIFO,and read FIFO described in Section 2.7 are all on the VCLK domain. From this, you can see that VCLKdrives the interface to the peripheral bus.

The MCLK domain consists of the DDR2 memory controller state machine and memory-mapped registers.This clock domain is clocked at the rate of the external DDR2 memory, PLL2_SYSCLK1/2.

To conserve power within the DDR2 memory controller, VCLK, MCLK, and PLL2_SYSCLK1 may bestopped. See Section 2.15 for proper clock stop procedures.

See the device-specific data manual for information describing the device memory-map.

The DDR2 memory controller signals are shown in Figure 3 and described in Table 2 . The followingfeatures are included:

•The maximum data bus is 32-bits wide.•The address bus is 15-bits wide with an additional 3 bank address pins.•Two differential output clocks driven by internal clock sources.•Command signals: Row and column address strobe, write enable strobe, data strobe, and data mask.•One chip select signal and one clock enable signal.

Figure 3. DDR2 Memory Controller Signals

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