Texas Instruments TMS320C6747 DSP Manuel utilisateur

TMS320C674x/OMAP-L1x ProcessorUniversal Serial Bus (USB1.1)OHCI Host Controller

User's Guide

Literature Number: SPRUFM8

June 2009

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Contents

Preface ........................................................................................................................................ 61 Introduction ......................................................................................................................... 81.1 Purpose of the Peripheral ................................................................................................ 82 Architecture ........................................................................................................................ 92.1 Clock and Reset .......................................................................................................... 92.2 Open Host Controller Interface Functionality ........................................................................ 102.3 Differences From OHCI Specification for USB ...................................................................... 102.4 Implementation of OHCI Specification for USB1.1 .................................................................. 112.5 OHCI Interrupts .......................................................................................................... 122.6 USB1.1 Host Controller Access to System Memory ................................................................ 122.7 Physical Addressing ..................................................................................................... 123 Registers ........................................................................................................................... 133.1 OHCI Revision Number Register (HCREVISION)................................................................... 143.2 HC Operating Mode Register (HCCONTROL) ...................................................................... 143.3 HC Command and Status Register (HCCOMMANDSTATUS) .................................................... 163.4 HC Interrupt and Status Register (HCINTERRUPTSTATUS) ..................................................... 173.5 HC Interrupt Enable Register (HCINTERRUPTENABLE) .......................................................... 183.6 HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................ 193.7 HC HCAA Address Register (HCHCCA) ............................................................................. 203.8 HC Current Periodic Register (HCPERIODCURRENTED) ........................................................ 203.9 HC Head Control Register (HCCONTROLHEADED) ............................................................... 213.10 HC Current Control Register (HCCONTROLCURRENTED) ...................................................... 223.11 HC Head Bulk Register (HCBULKHEADED) ........................................................................ 233.12 HC Current Bulk Register (HCBULKCURRENTED) ................................................................ 233.13 HC Head Done Register (HCDONEHEAD) .......................................................................... 243.14 HC Frame Interval Register (HCFMINTERVAL) .................................................................... 243.15 HC Frame Remaining Register (HCFMREMAINING) .............................................................. 253.16 HC Frame Number Register (HCFMNUMBER) ..................................................................... 253.17 HC Periodic Start Register (HCPERIODICSTART) ................................................................. 263.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD) ......................................................... 273.19 HC Root Hub A Register (HCRHDESCRIPTORA) .................................................................. 283.20 HC Root Hub B Register (HCRHDESCRIPTORB) .................................................................. 293.21 HC Root Hub Status Register (HCRHSTATUS) ..................................................................... 303.22 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) ................................................. 313.23 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) ................................................. 33

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List of Figures

1 Relationships Between Virtual Address Physical Address ............................................................ 122 OHCI Revision Number Register (HCREVISION) ..................................................................... 143 HC Operating Mode Register (HCCONTROL) ......................................................................... 144 HC Command and Status Register (HCCOMMANDSTATUS) ....................................................... 165 HC Interrupt and Status Register (HCINTERRUPTSTATUS) ........................................................ 176 HC Interrupt Enable Register (HCINTERRUPTENABLE) ............................................................ 187 HC Interrupt Disable Register (HCINTERRUPTDISABLE) ........................................................... 198 HC HCAA Address Register (HCHCCA) ................................................................................ 209 HC Current Periodic Register (HCPERIODCURRENTED) ........................................................... 2010 HC Head Control Register (HCCONTROLHEADED) ................................................................. 2111 HC Current Control Register (HCCONTROLCURRENTED) ......................................................... 2212 HC Head Bulk Register (HCBULKHEADED) ........................................................................... 2313 HC Current Bulk Register (HCBULKCURRENTED) ................................................................... 2314 HC Head Done Register (HCDONEHEAD) ............................................................................. 2415 HC Frame Interval Register (HCFMINTERVAL) ....................................................................... 2416 HC Frame Remaining Register (HCFMREMAINING) ................................................................. 2517 HC Frame Number Register (HCFMNUMBER) ........................................................................ 2518 HC Periodic Start Register (HCPERIODICSTART) .................................................................... 2619 HC Low-Speed Threshold Register (HCLSTHRESHOLD) ........................................................... 2720 HC Root Hub A Register (HCRHDESCRIPTORA) .................................................................... 2821 HC Root Hub B Register (HCRHDESCRIPTORB) .................................................................... 2922 HC Root Hub Status Register (HCRHSTATUS) ....................................................................... 3023 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) .................................................... 3124 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) .................................................... 33

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List of Tables

1 USB1.1 Host Controller Registers ....................................................................................... 132 OHCI Revision Number Register (HCREVISION) Field Descriptions ............................................... 143 HC Operating Mode Register (HCCONTROL) Field Descriptions ................................................... 154 HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions ................................ 165 HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions.................................. 176 HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions ...................................... 187 HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions ..................................... 198 HC HCAA Address Register (HCHCCA) Field Descriptions .......................................................... 209 HC Current Periodic Register (HCPERIODCURRENTED) Field Descriptions ..................................... 2010 HC Head Control Register (HCCONTROLHEADED) Field Descriptions ........................................... 2111 HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions ................................... 2212 HC Head Bulk Register (HCBULKHEADED) Field Descriptions ..................................................... 2313 HC Current Bulk Register (HCBULKCURRENTED) Field Descriptions ............................................ 2314 HC Head Done Register (HCDONEHEAD) Field Descriptions ...................................................... 2415 HC Frame Interval Register (HCFMINTERVAL) Field Descriptions ................................................. 2416 HC Frame Remaining Register (HCFMREMAINING) Field Descriptions ........................................... 2517 HC Frame Number Register (HCFMNUMBER) Field Descriptions .................................................. 2518 HC Periodic Start Register (HCPERIODICSTART) Field Descriptions ............................................. 2619 HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions ..................................... 2720 HC Root Hub A Register (HCRHDESCRIPTORA) Field Descriptions .............................................. 2821 HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions .............................................. 2922 HC Root Hub Status Register (HCRHSTATUS) Field Descriptions ................................................. 3023 HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions ............................. 3124 HC Port 2 Status and Control Register (HCRHPORTSTATUS2) Field Descriptions ............................. 33

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Preface

SPRUFM8 – June 2009

Read This First

About This Manual

This document describes the universal serial bus OHCI host controller.

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320C674x Digital Signal Processors (DSPs) and OMAP-L1xApplications Processors. Copies of these documents are available on the Internet at www.ti.com .Tip:Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DSP, related peripherals, and other technical collateral, isavailable in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUGM5 —TMS320C6742 DSP System Reference Guide. Describes the C6742 DSP subsystem,system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller(PSC), power management, and system configuration module.

SPRUGJ0 —TMS320C6743 DSP System Reference Guide. Describes the System-on-Chip (SoC)including the C6743 DSP subsystem, system memory, device clocking, phase-locked loopcontroller (PLLC), power and sleep controller (PSC), power management, and system configurationmodule.

SPRUFK4 —TMS320C6745/C6747 DSP System Reference Guide. Describes the System-on-Chip(SoC) including the C6745/C6747 DSP subsystem, system memory, device clocking, phase-lockedloop controller (PLLC), power and sleep controller (PSC), power management, and systemconfiguration module.

SPRUGM6 —TMS320C6746 DSP System Reference Guide. Describes the C6746 DSP subsystem,system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller(PSC), power management, and system configuration module.

SPRUGJ7 —TMS320C6748 DSP System Reference Guide. Describes the C6748 DSP subsystem,system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller(PSC), power management, and system configuration module.

SPRUG84 —OMAP-L137 Applications Processor System Reference Guide. Describes theSystem-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, deviceclocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), powermanagement, ARM interrupt controller (AINTC), and system configuration module.

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Related Documentation From Texas Instruments

SPRUGM7 —OMAP-L138 Applications Processor System Reference Guide. Describes theSystem-on-Chip (SoC) including the ARM subsystem, DSP subsystem, system memory, deviceclocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), powermanagement, ARM interrupt controller (AINTC), and system configuration module.

SPRUFK9 —TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Providesan overview and briefly describes the peripherals available on the TMS320C674x Digital SignalProcessors (DSPs) and OMAP-L1x Applications Processors.

SPRUFK5 —TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

SPRUFE8 —TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with addedfunctionality and an expanded instruction set.

SPRUG82 —TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory cachesand describes how the two-level cache-based internal memory architecture in the TMS320C674xdigital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintaincoherence with external memory, how to use DMA to reduce memory latencies, and how tooptimize your code to improve cache efficiency. The internal memory architecture in the C674xDSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and adedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level cachescan complete without CPU pipeline stalls. If the data requested by the CPU is not contained incache, it is fetched from the next lower memory level, L2 or external memory.

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1 Introduction

1.1 Purpose of the Peripheral

User's GuideSPRUFM8 – June 2009

Universal Serial Bus OHCI Host Controller

This document describes the universal serial bus OHCI host controller.

The USB1.1 OHCI host controller (HC) is a single port controller that communicates with USB devices atthe USB low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) datarates. It is compatible with the Universal Serial Bus Specification Revision 2.0 and the Open HCI—OpenHost Controller Interface Specification for USB, Release 1.0a, available through the Compaq ComputerCorporation web site, and hereafter called the OHCI Specification for USB. It is assumed that users of theUSB1.1 host controller are already familiar with the USB Specification and OHCI Specification for USB.

The USB1.1 host controller implements the register set and makes use of the memory data structuresdefined in the OHCI Specification for USB. These registers and data structures are the mechanisms bywhich a USB host controller driver software package can control the USB1.1 host controller. The OHCISpecification for USB also defines how the USB host controller implementation must interact with thoseregisters and data structures in system memory.

To reduce processor software and interrupt overhead, the USB1.1 host controller generates USB trafficbased on data structures and data buffers stored in system memory. The USB1.1 host controller accessesthese data structures without direct intervention by the processor using its bus master port. These datastructures and data buffers can be located in internal or external system RAM.

The USB1.1 host controller provides an interrupt to both the ARM and DSP.

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2 Architecture

2.1 Clock and Reset

2.1.1 Internal System Bus Clocks Needed

2.1.2 Local Bus Clock and Local Reset

2.1.3 48-MHz Reference Clock

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Architecture

The USB1.1 module requires that several different clocks are present before it can be accessed:1. Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4)2. Local bus clock to the USB1.1 host controller (derived from SYSCLK4)3. USB bus side 48-MHz reference clock must be present. Several options are available to source thisclock.

The internal system bus clocks SYSCLK2 and SYSCLK4 are normally configured during the device resetprocess; as the device PLL controller is initialized. The USB1.1 host controller operates in the SYSCLK4domain but SYSCLK2 since most of the device level bus infrastructure operates on the SYSCLK2 domain.Normally one or both of the host CPU clock domains (SYSCLK6 for the ARM and SYSCLK1 for the DSP)will be enabled as well.

The USB1.1 host controller actually operates from a local (gated) version of SYSCLK4. This allows themodule be put into a low power state when not in use. The module also has its own local reset that isasserted during a device level reset and remains asserted until released by software. Additionally softwarecan at any time assert a hardware reset on the USB1.1 host controller individually, causing it to reinitializewithout affecting any of the other peripherals on the device.

Both the local clock and local reset of the USB1.1 host controller are under the control of the device levelpower sleep controller 1 (PSC1) module. This module controls many local power sleep controller modules,and local power sleep controller 2 (LPSC2) of PSC1 controls the USB1.1 OHCI host controller.

This device includes an integrated USB 1.1 Phy for the OHCI Host Controller's Root Hub (Port 0). ThisPhy requires a 48-MHz reference clock for proper operation. Two options are available to provide thisreference clock:•Use the reference clock generated by the USB0 module integrated high-speed phy. The high-speedphy includes a phase locked loop (PLL) that is capable of generating a 48-MHz reference clock frommultiple different input clock options. This method is probably the most convenient as it does notrequire an externally sourced clock, and the PLL in the USB0 module has flexibility in the frequency ofits input clock. However when using this option, the USB0 phy must be operating in order to use theUSB1.1 OHCI host controller. (This does not mean that the USB2.0 module must be running, only thatits phy needs to be configured properly and enabled).•Provide the 48 MHz clock externally, on the USB_REFCLKIN pin.

For details on device-level configuration of the 48-MHz reference clock, see the device clocking chapter inyour device-specific System Reference Guide.

The USB1.1 host controller completes its reset after the host controller clock is transitioned from disabledto enabled and the host controller reset is removed. After system software turns on the clock to theUSB1.1 host controller and removes it from reset, it is necessary to wait until the USB1.1 host controllerinternal reset completes. To ensure that the USB1.1 host controller has completely reset, system softwaremust wait until reads of both the HCREVISION register and the HCHCCA register return their correct resetdefault values.

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2.2 Open Host Controller Interface Functionality

2.2.1 OHCI Controller Overview

2.3 Differences From OHCI Specification for USB

2.3.1 Power Switching Output Pins Not Supported

2.3.2 Overcurrent Protection Input Pins Not Supported

2.3.3 No Ownership Change Interrupt

Architecture

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The Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a defines a set ofregisters and data structures stored in system memory that control how a USB host controller interfaces tosystem software. This specification, in conjunction with the Universal Serial Bus Specification Version 2.0,defines most of the USB functionality that the USB1.1 host controller provides.

The OHCI Specification for USB focuses on two main aspects of the USB host controller hardwareimplementation: its register set and the memory data structures that define the appearance of USB busactivity. Other topics include interrupt generation, USB host controller state, USB frame management, andthe hardware methods used to process the lists of data structures in system memory.

This document does not duplicate the information presented in the OHCI Specification for USB or the USBSpecification. USB1.1 host controller users can refer to the USB Specification and the OHCI Specificationfor USB for detailed discussions of USB requirements and OHCI controller operation.

The USB1.1 module OHCI compatible host controller implementation does not implement every aspect ofthe functionality defined in the OHCI Specification for USB. The differences focus on power switching,overcurrent reporting, and the OHCI ownership change interrupt. Other restrictions are imposed by theeffects of the pin multiplexing options.

The device does not provide pins that can be controlled directly by the USB1.1 host controller OHCI portpower control features. The OHCI RHPORTSTATUS register port power control bits can be programmedby the USB1.1 host controller driver software, but this does not have any direct effect on any VBUSswitching implemented on the board.

You can use software control of GPIO pins or other implementation-specific control mechanisms to controlVBUS switching.

The device does not provide any pins that allow the USB1.1 host controller OHCI RHPORTSTATUSovercurrent protection status bits to be directly controlled by external hardware.

You can use software monitoring of GPIO pins or other implementation-specific control mechanisms toreport port overcurrent information to the USB1.1 host controller driver.

The USB1.1 host controller does not implement the OHCI ownership change interrupt.

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