Tews Technologies TPMC310 Manuel utilisateur

The Embedded I/O Compan

TPMC310

Conduction Cooled PMC

Isolated 2 x CAN Bus

Version 1.1

User Manual

Issue 1.1.5

January 2011

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7 25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0 Fax: +49 (0) 4101 4058 19

e-mail: [email protected] www.tews.com

TPMC310 User Manual Issue 1.1.5 Page 2 of 22

TPMC310-10

Conduction Cooled PMC, isolated 2 x CAN Bus,

P14 back I/O

This document contains information, which is

proprietary to TEWS TECHNOLOGIES GmbH. Any

reproduction without written permission is forbidden.

TEWS TECHNOLOGIES GmbH has made any

effort to ensure that this manual is accurate and

complete. However TEWS TECHNOLOGIES GmbH

reserves the right to change the product described

in this document at any time without notice.

TEWS TECHNOLOGIES GmbH is not liable for any

damage arising out of the application or use of the

device described herein.

Style Conventions

Hexadecimal characters are specified with prefix 0x,

i.e. 0x029E (that means hexadecimal value 029E).

For signals on hardware products, an ‚Active Low’ is

represented by the signal name with # following, i.e.

IP_RESET#.

Access terms are described as:

W Write Only

R Read Only

R/W Read/Write

R/C Read/Clear

R/S Read/Set

All trademarks mentioned are property of their

respective owners.

TPMC310 User Manual Issue 1.1.5 Page 3 of 22

Issue Description Date

1.0 Initial Issue October 2003

1.1 CAN Oscillator Frequency corrected (16 MHz) June 2004

1.2 New address TEWS LLC September 2006

1.3

Minor Version Step,

New PCB,

Added secondary thermal interface,

Added extra mounting holes preventing vibration,

MTBF value has changed,

Solder pad locations for termination options have changed.

April 2008

1.1.4 New Notation for User Manual and Engineering Documentation December 2008

1.1.5

(1) Corrected I/O Line Configuration Table

(2) Added note for the Bus_End Option

(3) Added note for supported baud rate range to Technical

Specification Table

January 2011

TPMC310 User Manual Issue 1.1.5 Page 4 of 22

Table of Contents

1PRODUCT DESCRIPTION.........................................................................................5

2TECHNICAL SPECIFICATION...................................................................................7

3LOCAL SPACE ADDRESSING..................................................................................8

3.1 PCI9030 Local Space Configuration .............................................................................................8

3.2 PLD Register Space........................................................................................................................8

3.2.1 CAN Control Register...........................................................................................................9

3.2.2 CAN Status Register...........................................................................................................10

3.2.3 CAN Controller Register Space..........................................................................................11

4PCI9030 TARGET CHIP...........................................................................................12

4.1 PCI Configuration Registers (PCR).............................................................................................12

4.1.1 PCI9030 PCI Header..........................................................................................................12

4.1.2 PCI Base Address Initialization ..........................................................................................13

4.2 Local Configuration Register (LCR)............................................................................................14

4.3 Configuration EEPROM................................................................................................................15

4.4 Local Software Reset....................................................................................................................16

5PROGRAMMING HINTS ..........................................................................................17

5.1 CAN Controller (SJA1000)............................................................................................................17

6CONFIGURATION HINTS........................................................................................19

6.1 I/O Line Configuration ..................................................................................................................19

6.2 Solder Pad Location .....................................................................................................................20

7PIN ASSIGNMENT...................................................................................................21

TPMC310 User Manual Issue 1.1.5 Page 5 of 22

List of Figures

FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6

FIGURE 6-1 : SOLDER PAD LOCATION.......................................................................................................20

List of Tables

TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................7

TABLE 3-1 : PCI9030 LOCAL SPACE CONFIGURATION ..............................................................................8

TABLE 3-2 : PLD REGISTER SPACE..............................................................................................................8

TABLE 3-3 : CAN CONTROL REGISTER........................................................................................................9

TABLE 3-4 : CAN STATUS REGISTER..........................................................................................................10

TABLE 3-5 : CAN CONTROLLER REGISTER SPACE..................................................................................11

TABLE 4-1 : PCI9030 PCI HEADER...............................................................................................................12

TABLE 4-2 : PCI9030 LOCAL CONFIGURATION REGISTER......................................................................14

TABLE 4-3 : CONFIGURATION EEPROM.....................................................................................................15

TABLE 5-1 : OUTPUT CONTROL REGISTER...............................................................................................17

TABLE 5-2 : CLOCK DIVIDER REGISTER ....................................................................................................18

TABLE 6-1 : I/O LINE CONFIGURATION......................................................................................................19

TABLE 6-2 : FACTORY DEFAULT I/O LINE CONFIGURATION...................................................................19

TABLE 7-1 : P14 I/O PIN ASSIGNMENT........................................................................................................22

TPMC310 User Manual Issue 1.1.5 Page 6 of 22

1 Product Description

The TPMC310 is a conduction cooled single-width 32 bit PMC module providing a two channel high

speed CAN bus interface.

The PLX Technology PCI9030 PCI Target Chip is used for the PCI bus interface.

Two Philips SJA1000 CAN Controllers (CAN specification 2.0B supported) are used for the CAN bus

interface (one for each channel).

The CAN bus I/O interface provides two independent channels, isolated from system logic and from

each other.

CAN High Speed transceivers are used for the CAN bus I/O interface.

An on board termination option (solder pads) is provided for each CAN bus channel allowing to

configure on board termination and/or pass trough mode for the CAN bus.

The TPMC310 uses the P14 I/O connector for the CAN bus I/O interface.

P11

P12

PCI9030

PCI Target

Chip

PLD

Logic

CAN CH2

Transceiver

CAN CH2

Power & Signal Isolation

CAN CH2

Term. Opt.

CAN CH1

Term. Opt.

SJA1000

CAN

Controller

SJA1000

CAN

Controller

CAN CH1

Power & Signal Isolation

CAN CH1

Transceiver

P14

Figure 1-1 : Block Diagram

TPMC310 User Manual Issue 1.1.5 Page 7 of 22

2 Technical Specification

Logic Interface

Mechanical Interface PCI Mezzanine Card (PMC) Interface

Conduction Cooled

Single Size

Electrical Interface PCI Rev. 2.1 compliant

33 MHz / 32 bit PCI

Universal PCI Signaling Voltage (3.3V PCI Signaling Voltage, 5V

PCI Signaling Voltage tolerant)

On board Devices

PCI Target Chip PCI9030 (PLX Technology)

CAN Controller 2 x SJA1000 (Philips) (16 MHz)

CAN Bus Transceiver 2 x TJA1050 (Philips)

I/O Interface

Number of CAN Bus

Channels 2 (isolated from system logic and from each other)

CAN Bus Interface CAN High Speed

The TJA1050 High-Speed CAN Transceiver supports baud rates

from 60 kbaud up to 1 Mbaud

I/O Connector PMC P14 I/O (64pin Mezzanine Connector)

Physical Data

Power Requirements 50mA typ @ + 3.3V DC

150mA typ @ + 5.0V DC

Temperature Range Operating :

Storage : -40°C to + 85°C

-55°C to +125°C

MTBF 372000 h

Weight 75g

Humidity 5 – 95 % non-condensing

Table 2-1 : Technical Specification

TPMC310 User Manual Issue 1.1.5 Page 8 of 22

3 Local Space Addressing

3.1PCI9030 Local Space Configuration

The local on board addressable regions are accessed from the PCI side by using the PCI9030 local

spaces.

PCI9030

Local

Space

PCI9030

PCI Base Address

(Offset in PCI

Configuration

Space)

PCI

Space

Mapping

Size

(Byte) Port

Width

(Bit)

Endian

Mode Description

0 2 (0x18) MEM 16 8 BIG PLD Register Space

1 3 (0x1C) MEM 512 8 BIG

CAN Controller

2 4 (0x20) - - - - Not Used

3 5 (0x24) - - - - Not Used

Table 3-1 : PCI9030 Local Space Configuration

3.2PLD Register Space

PCI Base Address :

PCI9030 PCI Base Address 2 (Offset 0x18 in PCI9030 PCI Configuration Register Space)

Offset to PCI

Base Address Register Name Size

(Bit)

0x00 CAN CONTROL REGISTER 8

0x01 CAN STATUS REGISTER 8

0x02 … 0x0F Reserved 8

Table 3-2 : PLD Register Space

TPMC310 User Manual Issue 1.1.5 Page 9 of 22

3.2.1 CAN Control Register

Bit Name Function Access Reset

7 :6 - Reserved (Undefined for reads, write as '0') - X

5 CAN2_INTEN

0 : CAN CH2 Interrupt Disabled

1 : CAN CH2 Interrupt Enabled R/W 0

4 CAN2_SEL

0 : CAN CH2 Transceiver Silent Mode

1 : CAN CH2 Transceiver Operating Mode R/W 0

3 CAN2_RST#

0 : CAN CH2 Controller Reset Mode

1 : CAN CH2 Controller Operating Mode R/W 0

2 CAN1_INTEN

0 : CAN CH1 Interrupt Disabled

1 : CAN CH1 Interrupt Enabled R/W 0

1 CAN1_SEL

0 : CAN CH1 Transceiver Silent Mode

1 : CAN CH1 Transceiver Operating Mode R/W 0

0 CAN1_RST#

0 : CAN CH1 Controller Reset Mode

1 : CAN CH1 Controller Operating Mode R/W 0

Table 3-3 : CAN Control Register

After power-up or board reset the CAN controllers are set to reset mode.

To set the CAN controllers to operating mode, the CANx_RST# bit must be set to ‘1’.

After power-up or board reset the CAN bus transceivers are set to silent mode.

To set the CAN bus transceivers to operating mode, the CANx_SEL bit must be set to ‘1’.

Disabling interrupts in the CAN Control Register only affects the interrupt mapping to the

PCI9030 LINTx# local interrupt inputs. It will not affect the interrupt source of the SJA1000 CAN

controllers.

If enabled, the CAN CH1 interrupt source is mapped to the PCI9030 LINT1# local interrupt input.

If enabled, the CAN CH2 interrupt source is mapped to the PCI9030 LINT2# local interrupt input.

The PCI9030 LINTx# local interrupt inputs are used in active low level sensitive mode.

The CAN interrupts must be acknowledged via SJA1000 registers (CAN Controller Register

Space).

Please see the SJA1000 CAN Controller Manual for more information.

TPMC310 User Manual Issue 1.1.5 Page 10 of 22

3.2.2 CAN Status Register

Bit Name Function Access Reset

7:2 - Reserved (Undefined for reads) - X

1 CAN2_INT CAN CH2 Controller Interrupt Request Status R X

0 CAN1_INT CAN CH1 Controller Interrupt Request Status R X

Table 3-4 : CAN Status Register

The CAN CHx controller interrupt request status is '0' for "no active interrupt request" and '1'

for "active interrupt request".

Please see the SJA1000 CAN Controller Manual for more information.

If enabled, the CAN CH1 interrupt source is mapped to the PCI9030 LINT1# local interrupt input.

If enabled, the CAN CH2 interrupt source is mapped to the PCI9030 LINT2# local interrupt input.

The PCI9030 LINTx# local interrupt inputs are used in active low level sensitive mode.

The CAN interrupts must be acknowledged via SJA1000 registers (CAN Controller Register

Space).

Please see the SJA1000 CAN Controller Manual for more information.

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