SpinCore Technologies DDS-I-300 Manuel utilisateur

PulseBlasterDDS™

Model DDS-I-300

(USB Board Version SP7)

Owner’s Manual

SpinCore Technologies, Inc.

htt ://www.s incore.com

PulseBlasterDDS-I-300

Congratulations and thank you for choosing a design from S inCore

Technologies, Inc.

We a reciate your business!

At S inCore we try to fully su ort the needs of our customers. If you are in

need of assistance, lease contact us and we will strive to rovide the

necessary su ort.

SpinCore Technologies, Inc. reserves the right to make changes to the prod ct(s) or information herein witho t notice.

P lseBlasterDDS™, P lseBlaster™, SpinCore, and the SpinCore Technologies, Inc. logos are trademarks of SpinCore Technologies, Inc. All other

trademarks are the property of their respective owners.

SpinCore Technologies, Inc. makes every effort to verify the correct operation of the eq ipment. This eq ipment version is not intended for se in a

system in which the fail re of a SpinCore device will threaten the safety of eq ipment or person(s).

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PulseBlasterDDS-I-300

Table of Contents

Table of Contents ................................................................................................................................... 3

I. Introduction ......................................................................................................................................... 4

Product Overview ....................................................................................................................................................... 4

Board Architecture ...................................................................................................................................................... 4

Block Diagram ....................................................................................................................................................... 4

Product S ecifications ................................................................................................................................................ 6

RF Out ut Level ........................................................................................................................................................... 7

II. Installation .......................................................................................................................................... 8

Installing the PulseBlasterDDS-I-300 ......................................................................................................................... 8

Testing the PulseBlasterDDS-I-300 ............................................................................................................................. 9

III. Using the PulseBlasterDDS-I-300 ................................................................................................. 11

Controlling the PulseBlasterDDS-I-300 with S inAPI .............................................................................................. 11

Frequency and Phase Registers ............................................................................................................................... 11

Sample Output ..................................................................................................................................................... 12

Sha e and Am litude Registers (AWG) ................................................................................................................... 14

Sample Output ..................................................................................................................................................... 14

Pulse Programs .......................................................................................................................................................... 16

Control lines ......................................................................................................................................................... 17

Triggering ................................................................................................................................................................... 18

Clock out ut on BNC0 ............................................................................................................................................... 18

Clock In ut Signal Standard ..................................................................................................................................... 19

IV. PCI Connection - Connecting to the PulseBlasterDDS-I-300-PCI boards ................................ 20

Connector Information .............................................................................................................................................. 20

BNC Connectors .................................................................................................................................................. 20

Long IDC Hea ers ............................................................................................................................................... 20

HWTrig/Reset Hea er .......................................................................................................................................... 21

V. USB Connection - Connecting to the PulseBlasterDDS-I-300-USB boards .............................. 22

Power Requirements ................................................................................................................................................. 22

Power Connectors .................................................................................................................................................... 22

Digital Out ut Connectors ....................................................................................................................................... 23

Header JP302 ............................................................................................................................................................ 25

Connector Locations ................................................................................................................................................. 25

VI. External Frequency Modulation .................................................................................................. 26

Hea er JP302 (Frequency Select an HW Trigger/Reset) ................................................................................... 26

Important Notes: .................................................................................................................................................. 27

VII. PulseBlasterDDS-I-300 Interface for LabVIEW .......................................................................... 27

Overview of S inCore LabVIEW GUI Interface ........................................................................................................ 27

Related Products and Accessories ................................................................................................... 28

Contact Information ............................................................................................................................. 29

Document Information ........................................................................................................................ 29

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PulseBlasterDDS-I-300

I. Introduction

Product Overview

P lseBlasterDDS is a high-performance signal generator that combines two nits – the digital waveform synthesis nit

(DDS, Direct Digital Synthesis), and the P lseBlaster Timing Processor.

The P lseBlaster Timing Processor provides all the necessary timing control signals req ired for overall system control

and p lse synchronization. This part of the P lseBlasterDDS design also generates the programmable-length digital (TTL

logic) p lses. By adding DDS feat res, P lseBlasterDDS can now provide not only programmable TTL p lses b t also

RF (Radio Freq ency) o tp t signals. By tilizing the P lseBlaster Timing Processor core, the combined system can

generate sophisticated p lse seq ences with single-clock acc racy, meeting high-performance demands of advanced

sers.

The P lseBlasterDDS-I-300 is eq ipped with one 300 MHz DAC (Digital-to-Analog Converter), and it can prod ce

sef l o tp t signal freq encies from DC (Direct C rrent) (0 Hz) to 100 MHz. Arbitrary Waveform Generation (AWG),

o tp t gating and atten ation, and ser-programmable amplit de, freq ency, and phase mod lation are standard. In

addition to the ability to mod late the envelope of the generated signal, the shape of the carrier signal can be c stom-

defined as well, giving the ser the opport nity to explore novel excitation modes. Select designs allow for external

freq ency mod lation sing dedicated hardware inp t lines.

Packaged in a small USB form factor, the P lseBlasterDDS-I-300 series of boards provide sers the ability to control

their systems thro gh the generation of f lly synchronized digital and analog excitation p lses, ranging from simple RF and

TTL p lses to sophisticated excitation schemes with nested loops, s bro tines, etc., providing sers with a compelling

price/performance proposition nmatched by any other device on the market today.

Please note that c rrently, the PCI board version SP6 is only available for special orders.

Board Architecture

Block Diagram

Fig re 1, on the next page, presents the general architect re of the P lseBlasterDDS-I-300 board. The two major

b ilding blocks are the DDS Core (top level blocks in Fig re 1), and the P lseBlaster Timing Core (PB Core, bottom level

of blocks in Fig re 1).

The DDS Core contains a N merically Controlled Oscillator (NCO) that is eq ipped with programmable freq ency and

phase registers that are nder the p lse program control thro gh the P lseBlaster Timing Core. Following the NCO, the

Arbitrary Waveform Generator (AWG) nit can mod late the signal envelope to a ser programmable shape, e.g., a sinc

shape. Scaling, or atten ation of the signal amplit de, is also nder program control, as well as the additional gating

(blanking) in the digital domain.

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PulseBlasterDDS-I-300

The PB Core controls the timing of the gating p lses and provides the necessary control signals for freq ency, phase,

shape and amplit de registers. The PB Core also o tp ts TTL signals to the o tside world, as programmed by the ser.

The PB processor core exec tes instr ctions as written by the ser and stored in the on-chip SRAM mod le, and, once

programmed, the processor operates a tonomo sly.

The DDS and PB cores are driven from a common clock so rce (the 50 MHz1 Reference Clock in Fig re 1). The on-

board clock so rce is removable and, in lie of the on-board clock, any 3.3 V TTL compatible clock so rce of arbitrary

stability can be sed.

The DDS and PB cores have been integrated onto a single silicon chip. High performance DAC chip and high-c rrent

o tp t amplifier complement the design. User control of the system is provided thro gh the host-programming interface

over the PCI b s or USB controller.

1A 75 MHz clock may be sed with the P lseBlasterDDS-I-300.

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Figure 1: P lseBlasterDDS-I-300 Board Architect re.

PulseBlasterDDS-I-300

Product S ecifications

Parameter Min Typ Max Units

Analog O tp t D/A sampling rate 300 MHz

D/A sampling precision 14 bits

O tp t voltage range (peak-peak) 1 - 4 (1) -V

Phase resol tion 0.09(2) -deg.

Freq ency resol tion 1.11(3) -Hz

RF O tp t (8) DC (0 Hz) 100 MHz

Digital O tp t N mber of digital o tp ts 4(4) 9

Logical 1 o tp t voltage 3.3(5) -V

Logical 0 o tp t voltage 0-V

O tp t drive c rrent 25 mA

Rise/Fall time 1 -ns

Digital Inp t

(HW_Trig,HW_Reset)

Logical 1 inp t voltage 1.7 4.1 V

Logical 0 inp t voltage -0.5 0.7 V

P lse Program # of instr ction words 1024 to 4096(6) -words

P lse resol tion 13.3(7) -ns

Instr ction length 66.6 ns 693 days

Table 1: P lseBlasterDDS-I-300 Prod ct Specifications.

Notes

1) Analog o tp t voltage is factor adj stable p to 4 Vpp at 10 MHz. See RF O tp t Level section on the next page

for more information.

2) Phase-offset control word is 12-bit wide.

3) Ass ming a 50 MHz reference clock and a 300 MHz NCO freq ency. Freq ency control word is 28-bit wide.

4) On PCI boards, all 24 control bits are ro ted to on-board IDC header, and signals that are not sed internally can

be tilized to control o tside devices. Please contact SpinCore if yo req ire more digital o tp ts; c stom

designs with more o tp t bits may be available.

5) This is the val e seen witho t sing termination. When the line is terminated with 50 Ω, the o tp t voltage will be

lower.

6) This n mber can be larger on USB boards. Please contact SpinCore for c stom design feat ring a larger n mber

of instr ction words.

7) Ass ming a 50 MHz reference clock and a 75 MHz P lseBlaster timing core freq ency.

8) The RF o tp t can operate from direct c rrent - DC (0 Hz) to 100 MHz. The analog o tp t is DC co pled.

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PulseBlasterDDS-I-300

RF Out ut Level

There are c rrently two different options for P lseBlasterDDS-I-300 RF analog o tp t amplifier – the standard gain and

the high gain. Fig re 2, below shows the typical freq ency characteristics of the analog o tp t signals for the two o tp t

options. The standard-gain P lseBlasterDDS-I-300 for a 50 Ω load has an o tp t voltage of 1 Volt peak-to-peak at 10

MHz, with a 3 dB bandwidth of abo t 85 MHz. The high-gain amplifier with a 50 Ω load has a maxim m o tp t voltage of

abo t 3.75 Volts peak-to-peak, with a 3 dB bandwidth of abo t 21 MHz, while covering the same freq ency range as the

standard-gain board.

Please note, the s stained analog o tp t voltage feat re is only available on PCI boards. To obtain a s stained

analog o tp t voltage, set the freq ency register to 0.0 Hz, and se the content of the phase registers to control the act al

o tp t voltage level.

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Figure 2: P lseBlasterDDS-I-300 analog o tp t voltage vs. o tp t freq ency. The

dotted line represents the standard-gain o tp t amplifier, and the solid line

represents the high-gain o tp t amplifier. The voltage val es are for a 50 Ohm

load impedance. The zero dBm o tp t val e for both amplifiers occ rs at

approximately 90 MHz.

0 20 40 60 80 100 120

0

0.5

1

1.5

2

2.5

3

3.5

4

High Gain

Standard Gain

Freq ency (MHz)

Voltage (volts pk-pk on 50 Ohms)

PulseBlasterDDS-I-300

II. Installation

Installing the PulseBlasterDDS-I-300

To install the board yo m st complete the following three steps:

1. Download and install the latest SpinAPI software package and example programs on yo r comp ter. These are

available at: http://www.spincore.com/s pport/spinapi/

•SpinAPI is a c stom Application Programming Interface (API) package developed by SpinCore Technologies,

Inc. SpinAPI is designed to be sed only with SpinCore Technologies, Inc. prod cts. SpinAPI can be tilized

sing C/C++, or LabVIEW (described in Section VII).

•SpinAPI contains device drivers and example programs. A shortc t to the location of these files is created

a tomatically in the Windows Start Men at “Start>Programs>S inCore”. See the “readme.txt” file in this

location for more information.

2. Sh t down the comp ter

•For the PCI board: Insert the P lseBlasterDDS-I-300 card into an available PCI slot and fasten the PC

bracket sec rely with a screw.

•For the USB board: Pl g one end of the USB cable into the P lseBlasterDDS-I-300 board and the other

end into the host comp ter. Next, power the board thro gh the 5-pin DIN-type connector or 6-position

Molex-style connector. We recommend p rchasing the RadioProcessorUSB Power S pply, which has the

6-pin o tp t connector and is pin-compatible with the power connector of the PBDDS-I-300-USB board.

For more information on powering the P lseBlasterDDS-I-300 USB board please read Power Connectors

in Section V. USB Connection - Connecting to the P lseBlasterDDS-I-300-USB boards.

•Warning: Do not connect PEG (PCI Express Graphics) power connectors available in some comp ters

directly to the 6-position Molex-style power connector. Doing so will ca se irreparable damage to the

board. SpinCore Technologies is not liable for any damage ca sed by this.

3. T rn on the comp ter and follow the installation prompts. Windows may recognize yo r board as a

RadioProcessor board b t the board will still f nction as it sho ld, as the f nctionality of the PBDDS-I-300 is a s b-

set of the f nctionality of the RadioProcessor.

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PulseBlasterDDS-I-300

Testing the PulseBlasterDDS-I-300

Once yo r board is installed properly, the f nctionality of the device can be tested sing three example programs

available from the SpinCore website. All o tp t seq ences generated by test programs can be verified sing an

oscilloscope.

If yo are sing a high inp t impedance oscilloscope to monitor the P lseBlasterDDS-I-300's o tp t, place a resistor

that matches the characteristic impedance of the transmission line in parallel with the coaxial transmission line at the

oscilloscope inp t by attaching it to the line thro gh a T-Adapter(e.g., a 50 Ω resistor with a 50 Ω transmission line, see

Fig res 3 and 4 below). For ease of observing the p lsed RF signals, the oscilloscope sho ld be triggered by any of the

TTL o tp ts. When sing an oscilloscope with an adj stable bandwidth, set the bandwidth to as large as possible. Fail re

to do so may yield inacc rate reado ts on the oscilloscope.

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Figure 3: Left: BNC T-Adapter and Right: BNC 50 Ohm

resistor.

PulseBlasterDDS-I-300

The first program is pbdds_i_300_excite_test. This will prod ce a 1.0 MHz sine wave on the Analog O t connection and

a logical high signal on the Digital O t connection - these signals will t rn on for 10 μs and off for 1 ms and will be repeated

indefinitely. The Digital O t on the oscilloscope can be sed to trigger the capt re of the analog signal.

The signal o tp t can be stopped by sing the pb_stop.exe program. The corresponding pb_start.exe will restart the

PBDDS board. Reloading the board with a new program will also stop the exec tion of any r nning program.

Next, pbdds_i_300_phase_test will prod ce a 1.0 MHz o tp t on the Analog O t connection which will t rn on for 8 μs

and off for 1 ms. The sin wave will cycle thro gh 4 phase offset registers(one every 2 μs, 90 degrees apart) and will

repeat indefinitely.

To test the AWG feat re of the board, se pbdds_i_300_awg. This program will ask for two amplit de val es and one

freq ency val e, and then it will load the board to o tp t two sinc-shaped p lses, one with each amplit de val e. This will

repeat every 1 ms.

Along with the exec table programs, the folder also contains the C so rce code of all test programs. Any so rce code

can be modified, th s allowing the ser to start making c stomized programs as necessary. When SpinAPI tools are

installed on the comp ter, do ble-clicking any C so rce code will la nch a graphical integrated environment for easy

editing and reb ilding of new exec tables via the “Reb ild All” men f nctionality.

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Figure 4: BNC T-Adapter on oscilloscope with coaxial

transmission line connected on the left and BNC 50 Ohm

resistor connected on the right, to terminate the line.

SpinCore Technologies DDS-I-300 Manuel utilisateur

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