SMC Networks SMC91C95 Manuel utilisateur

SMC91C95

PRELIMINARY

ISA/PCMCIA Full Duplex Single-Chip

Ethernet and Modem Controller with RAM

FEATURES

• ISA/PCMCIA Single Chip Ethernet Controller

With Modem Support

• 6 Kbytes Built-In RAM

• Supports IEEE 802.3 (ANSI 8802-3) Ethernet

Standards

• Full Duplex Support

• Hardware Memory Management Unit

• Built-In AUI and 10BASE-T Network

Interfaces

• Simultasking - Early Transmit and Early

Receive Functions

• Advanced Power Management

Features/Including Magic Packet Frame

Control

• Software Compatible with SMC91C92/

SMC91C94 (in ISA Mode)

• Configuration Registers Implement Cardbus

Multi-Function Specification V3.0 with

Backward Compatibility to V2.1

• Interfaces Directly to Lucent Technologies and

Rockwell International Modem Chipsets

• On-Chip Attribute Memory (CIS) of up to 512

Bytes (On Even Addresses) For Card

Configuration Information; Expandable

Externally

• Option for Serial or Parallel EEPROM for CIS

• Optional External Flash Capability for XIP

(Execute in Place)

• Automatic Technology to Detect TX/RX

10BASE-T Tranceiver Pair Miswiring

• Low Power CMOS Design

• Supports Magic Packet Wakeup

• 128 Pin VTQFP Package

Bus Interface

• Direct Interface to ISA and PCMCIA with

No Wait States

• High Impedance Speaker Interface

• Flexible Bus Interface

• 16-Bit Data and Control Paths

• Fast Access Time (40 ns)

• Pipelined Data Path

• Handles Block Word Transfers for Any

Alignment

• High Performance Chained ("Back-to-

Back") Transmit and Receive

• Flat Memory Structure for Low CPU

Overhead

• Dynamic Memory Allocation Between

Transmit and Receive

• Buffered Architecture, Insensitive to Bus

Latencies (No Overruns/Underruns)

• Supports Boot PROM for Diskless ISA

Applications

Simultasking is a trademark and SMC is a registered trademark of Standard Microsystems Corporation

TABLE OF CONTENTS

FEATURES.......................................................................................................................................................1

PIN CONFIGURATION....................................................................................................................................3

GENERAL DESCRIPTION...............................................................................................................................4

OVERVIEW ......................................................................................................................................................4

PIN REQUIREMENTS......................................................................................................................................7

DESCRIPTION OF PIN FUNCTIONS..............................................................................................................9

BUFFERTYPES........................................................................................................................................... 17

FUNCTIONAL DESCRIPTION.......................................................................................................................21

INTERRUPT STRUCTURE............................................................................................................................32

RESET LOGIC.............................................................................................................................................. 33

POWERDOWN LOGIC................................................................................................................................ 34

PCMCIA ATTRIBUTE MEMORY: ADDRESS 0- 7FFEH............................................................................................ 35

PCMCIA CONFIGURATIONREGISTERS: ADDRESS 8000-803EH............................................................................. 35

INTERNAL VS EXTERNAL ATTRIBUTE MEMORY MAP.................................................................................................. 36

THEORY OF OPERATION............................................................................................................................69

“MAGIC PACKET” SUPPORT.................................................................................................................................. 70

INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP........................................................................ 80

PCMCIA CONFIGURATION REGISTERS DESCRIPTION....................................................................... 82

FUNCTIONAL DESCRIPTION OF THE BLOCKS...................................................................................... 91

BOARD SETUP INFORMATION............................................................................................................... 100

OPERATIONAL DESCRIPTION..................................................................................................................104

TIMING DIAGRAMS ....................................................................................................................................108

Related Documentation

1. PCMCIA 2.1 Standard (for PCMCIA timing and functionality)

2. PCMCIA 3.X spec (for multi-function extensions)

3. AT&T HSM288xCF Modem Chip Set Data Sheet - July 5, 1994

4. Rockwell RC224ATF and C39 Modem Chip Sets Designer’s Guide

Network Interface

• Integrates 10BASE-T Transceiver

Functions:

-Driver and Receiver

-Link Integrity Test

-Receive Polarity Detection and

Correction

• Integrates AUI Interface

• Implements 10 Mbps Manchester

Encoding/Decoding and Clock Recovery

• Automatic Retransmission, Bad Packet

Rejection, and Transmit Padding

• External and Internal Loopback Modes

• Four Direct Driven LEDs for Status/

Diagnostics

Software Drivers

• Uses Certified SMC9000 Drivers Which

Operate with Every Major Network

Operating System

• Software Driver Compatible with

SMC91C92, SMC91C94 and SMC91C100

(100 Mbps) Controllers in ISA Mode

• Software Driver Utilizes Full Capability of

32 Bit Microprocessor

PIN CONFIGURATION

AVDD

TXP/nCOLL

TXN/nCRS

TPETXP

TEPTXDP

TPETXN

TPETXDN

AVSS

nTXLED/nTXEN

nRXLED/RXCLK

nLINKLED/TXD

nBSELED/RXD

VDD

SPKRIN

SPKROUT

nMIS16

MRDY

MINT

VSS

MRINGIN

nMRINGOA

MRINGOB

nMCS

nMRESET

VDD

MIDLEN1

nMPWDN

nMPDOUT

MFBK1

VSS

AVSS

COLN

COLP

RECN

RECP

TPERXN

TPERXP

AVDD

AVSS

RBIAS

AVDD

nXENDEC

nEN16

PWRDWN/TXCLK

nROM/nPCMCIA

VSS

ENEEP

EESK

EECS

EEDO/SDOUT

EEDI

IOS2

IOS1

VDD

IOS0

XTAL2

XTAL1

WAKEUP

nWAKEUP_EN

RESET

VSS

INTR3

INTR2/nSTSCHG

INTR1/nINPACK

INTR0/nIREQ

VDD

nIORD

nIOWR

nMEMR/nOE

nIOSC16/nIOIS16

VSS

IOCHRDY/nWAIT

BALE/nWE

nSBHE/nCE2

VDD

D15

D14

D13

D12

VSS

D11

D10

VDD

VSS

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

SMC91C95

128 Pin VTQFP

AEN/nREG

VDD

VSS

A10

A11

A12

A13

VDD

A14

A15

A16/nFWE

A17/nFCS

A18

A19/nCE1

VSS

VDD

GENERAL DESCRIPTION

The SMC91C95 is a VLSI Ethernet Controller

that combines ISA and PCMCIA interfaces, as

well as an interface to a companion modem

chip set, in one chip. The SMC91C95

integrates all the MAC and physical layer

functions as well as the packet RAM needed to

implement a high performance 10BASE-T

(twisted pair) node. For 10BASE5 (thick coax),

10BASE2 (thin coax), and 10BASE-F (fiber)

implementations, the SMC91C95 interfaces to

external transceivers via its AUI port. Only one

additional IC is required on most applications.

The SMC91C95 occupies 16 I/O locations and

no memory space except for PCMCIA attribute

memory space. The same I/O space is used for

both ISA and PCMCIA operations. The

SMC91C95 can directly interface the ISA and

PCMCIA buses and deliver no wait state

operation. Its shared memory is sequentially

accessed with 40ns access times to any of its

registers, including its packet memory. No

DMA services are used by the SMC91C95;

virtually decoupling network traffic from local or

system bus utilization. For packet memory

management, the SMC91C95 integrates a

unique hardware Memory Management Unit

(MMU) with enhanced performance and

decreased software overhead when compared

to ring buffer and linked list architectures. The

SMC91C95 is portable to different CPU and bus

platforms due to its flexible bus interface, flat

memory structure (no pointers), and its loosely

coupled buffered architecture (not sensitive to

latency).

The SMC91C95 interfaces directly with

Rockwell International L39/C39 controller-based

modems and Lucent Technologies’

HSM288xCF modem.

OVERVIEW

A unique architecture allows the SMC91C95 to

combine high performance, flexibility, high

integration and simple software interface.

The SMC91C95 incorporates the SMC91C92/4

functionality for ISA environments with several

new features, as well as a PCMCIA interface

and attribute registers that comply with the

PCMCIA Multi-Function specification. Mode

selection between ISA and PCMCIA is static

and is done only once at the end of power on

reset. The SMC91C95 consists of the same

logical I/O register structure in ISA and

PCMCIA modes. However, some of the signals

used to access the PCMCIA differ from the ISA

mode. Additional registers exist in the PCMCIA

attribute space. The ROM memory space only

exists in ISA mode and the attribute space only

exists in PCMCIA mode.

I/O decoders are included in the SMC91C95’s

PCMCIA interface, with independent decoders

for the LAN and for the modem functions.

These decoders are used whenever the

SMC91C95 is used as a multi-function card,

and they can be bypassed when only one

function is enabled. The SMC91C95 also

merges the LAN’s internal interrupt source with

the external modem interrupt connected to the

SMC91C95.

The MMU (Memory Management Unit)

architecture used by the SMC91C95 combines

the simplicity and low overhead of fixed areas

with the flexibility of linked lists providing

improved performance over other methods.

The SMC91C95 is designed to support full

duplex switched Ethernet where transmit and

receive are fully independent. It has 6 kbytes of

internal memory and the MMU manages

memory in 256 byte pages. The memory size

accommodates the increase in interrupt latency

resulting from simultaneous LAN and modem

operation as well as the potential for

simultaneous transmit and receive traffice in

some full duplex applications.

Packet reception and transmission are

determined by memory availability. All other

resources are always available if memory is

available. To complement this flexible

architecture, all ISA bus interface functions are

incorporated in the SMC91C95, as well as a

4608 byte packet RAM and serial EEPROM-

based setup. The user can select or modify

configuration choices.

The SMC91C95 stores the Configuration

Information Structure (CIS) on reset or power-

up from the serial EEPROM. This allows the

host to access data to allow the setup of the

PCMCIA multi-function card.

In ISA mode, the serial EEPROM acts as

storage for configuration and IEEE Ethernet

address information compatible with the existing

SMC9000 family of ISA Ethernet controllers.

In PCMCIA mode, the serial EEPROM stores

the CIS, as well as the IEEE address,

information, but it does not store any I/O or IRQ

information since this information is handled by

the host’s socket controller. For CIS

requirements above 512 bytes, an optional

external parallel EEPROM can be used in

conjunction with the internal CIS. This allows

additional external, non-volatile storage for

applications that require XIP and use the

modem function. If the serial EEPROM is not

used in PCMCIA mode, the parallel EEPROM

must be used. In this case, the parallel

EEPROM is selected for the first 512 bytes of

storage as well, allowing the CIS to be stored in

the parallel EEPROM and, on power-up, to be

read directly by the host. The remaining

parallel EEPROM can be used for XIP

applications, if needed.

The SMC91C95 integrates most of the 802.3

functionality, incorporating the MAC layer

protocol, the physical layer encoding and

decoding functions with the ability to handle the

AUI interface. For twisted pair networks, the

SMC91C95 integrates the twisted pair

transceiver as well as the link integrity test

functions.

The SMC91C95 is a true 10BASE-T single chip

able to interface a system or a local bus.

Directly-driven LEDs for installation and run-

time diagnostics are provided, as well as 802.3

statistics gathering to facilitate network

management.

The SMC91C95 offers:

High integration:

Single chip adapter including:

Packet RAM

ISA bus interface

PCMCIA interface

EEPROM interface

Encoder decoder with AUI interface

Full duplex, magic packet 10BASE-T

transceiver

Lucent Technologies and Rockwell

International modem interface

High performance:

Chained (“back-to-back”) packet handling

with no CPU intervention:

Queues transmit packets

Queues receive packets

Full duplex operation for higher

network throughput

Stores results in memory along with

packet

Queues Ethernet and modem

interrupts

Optional single interrupt upon

completion of transmit chain

Fast block move operation for load/unload:

CPU sees packet bytes as if stored

contiguously

Handles 16 bit transfers regardless of

address alignment

Access to packet through fixed window

Fast bus interface:

Compatible with ISA type and faster buses

Flexibility:

Flexible packet and header processing:

Can be set to Simultasking - Early

Receive and transmit modes

Can access any byte in the packet

Can immediately remove undesired

packets from queue

Can move packets from receive to

transmit queue

Can alter receive processing order

without copying data

Can discard or enqueue again a failed

transmission

Resource allocation:

Memory dynamically allocated for transmit

and receive

Can automatically release memory on

successful transmission

Configuration:

ISA:Uses non-volatile jumperless setup via

serial EEPROM

PCMCIA:

Uses serial EEPROM for attribute

memory storage. PCMCIA I/O ignores

address lines A4-A15 and relies on the

PCMCIA host, decoding for the slot

nROM/nPCMCIA on the SMC91C95 is left

open with a pullup for ISA mode. This pin

is sampled at the end of Power On Reset.

If found low, the SMC91C95 is configured

for PCMCIA mode.

PIN REQUIREMENTS

FUNCTION ISA PCMCIA NUMBER OF

PINS

SYSTEM ADDRESS BUS A0-A15

A16

A17

A18

A19

AEN

A0-A15

nFWE

nFCS

nCE1

nREG

SYSTEM DATA BUS D0-D15 D0-D15 16

SYSTEM CONTROL BUS RESET

BALE

nIORD

nIOWR

nMEMR

IOCHRDY

nIOCS16

nSBHE

INTR0

INTR1

INTR2

INTR3

RESET

nWE

nIORD

nIOWR

nOE

nWAIT

nIOIS16

nCE2

nIREQ

nINPACK

nSTSCHG

MODEM INTERFACE nMRESET

MINT

nMCS

MRDY

nMPWDN

MIDLEN1

MRINGIN

nMRINGOA

MRINGOB

SPKRIN

SPKROUT

nMPDOUT

MFBK1

nMIS16

nMRESET

MINT

nMCS

MRDY

nMPWDN

MIDLEN1

MRINGIN

nMRINGOA

MRINGOB

SPKRIN

SPKROUT

nMPDOUT

MFBK1

nMIS16

SERIAL EEPROM EEDI

EEDO

EECS

EESK

ENEEP

IOS0

IOS1

IOS2

EEDI

EEDO

EECS

EESK

ENEEP

IOS0

IOS1

IOS2

FUNCTION ISA PCMCIA NUMBER OF

PINS

CRYSTAL OSC. XTAL1

XTAL2 XTAL1

XTAL2 2

POWER VDD

AVDD VDD

AVDD 12

GROUND GND

AGND GND

AGND 12

10BASE-T INTERFACE TPERXP

TPERXN

TPETXP

TPETXN

TPETXDP

TPETXDN

TPERXP

TPERXN

TPETXP

TPETXN

TPETXDP

TPETXDN

AUI INTERFACE RECP

RECN

COLP

COLN TXP/nCOLL

TXN/nCRS

RECP

RECN

COLP

COLN

TXP/nCOLL

TXN/nCRS

LEDs nLNKLED/TXD

nRXLED/RXCLK

nBSELED/RXD

nTXLED/nTXEN

nLNKLED/TXD

nRXLED/RXCLK

nBSELED/RXD

nTXLED/nTXEN

MISC. RBIAS

WAKEUP

nWAKEUPEN

PWRDWN/TXCLK

nXENDEC

nEN16

ROM/nPCMCIA

RBIAS

WAKEUP

nWAKEUPEN

PWRDWN/TXCLK

nXENDEC

nEN16

ROM/nPCMCIA

TOTAL PINS 120

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL TYPE DESCRIPTION

113 nROM/

nPCMCIA I/O4 with

pullup This pin is sampled at the end of RESET.

When this pin is sampled low the SMC91C95

is configured for PCMCIA operation and all

pin definitions correspond to the PCMCIA

mode. For ISA operation this pin is left open

and is used as a ROM chip select output that

goes active when nMEMR is low and the

address bus contains a valid ROM address.

35, 36,

38-43,

45-50,

52, 53

Address 0-

15 A0-A15 IInput address lines 0 through 15.

54 Address 16 A16 IISA - Input address line 16.

nFlash

Memory

Write

nFWE O4 PCMCIA - Output. Flash Memory Write

Enable used for programming the attribute

memory. Goes active (low) when nWE=0 and

WRATTRIB=1 (in ECOR bit 3).

55 Address 17 A17 IISA - Input address line 17.

nFlash

Memory

Chip Select

nFCS O4 PCMCIA - Output. Flash Memory Chip Select

used to access attribute memory. Goes active

(low) when nREG=0, nCE1=0 and A15=0.

56 Address 18 A18 IInput address line 18.

57 Address 19 A19 I with pullup ISA - Input address line 19.

Card Enable

1nCE1 PCMCIA - Card Enable 1 input. Used to

select card on even byte accesses.

34 Address

Enable AEN I with pullup ISA - Address enable input. Used as an

address qualifier. Address decoding is only

enabled when AEN is low.

nREG PCMCIA - Attribute memory and IO select

input. Asserted when the card attribute space

or IO space is being accessed.

DESCRIPTION OF PIN FUNCTIONS

PIN NO. NAME SYMBOL TYPE DESCRIPTION

81 nByte High

Enable nSBHE I with pullup ISA - Byte High Enable input. Asserted (low)

by the system to indicate a data transfer on

the upper data byte.

nCard

Enable 2 nCE2 PCMCIA - Card Enable 2 input. Used to

select card on odd byte accesses.

83 Ready IOCHRDY OD24 with

pullup ISA - Output. Optionally used by the

SMC91C95 to extend host cycles.

nWait nWAIT PCMCIA - Output. Optionally used by the

SMC91C95 to extend host cycles.

59, 60,

61, 63,

65, 66,

68-70,

72-74,

76-79

Data Bus D0-D15 I/O24 Bidirectional. 16 bit data bus used to access

the SMC91C95 internal registers. The data

bus has weak internal pullups. Supports direct

connection to the system bus without external

buffering.

98 Reset RESET IS with

pullup Input. Active high Reset. This input is not

considered active unless it is active for at least

100ns to filter narrow glitches. A POR circuit

generates an internal reset upon power up for

at least 15msec. All hardware reset

references in this spec relate to the OR

function of the POR and the RESET pin.

82 Address

Latch BALE IS with

pullup ISA - Input. Address strobe. For systems that

require address latching, the falling edge of

BALE latches address lines and nSBHE.

nWrite

Enable nWE PCMCIA - Write Enable input. Used for

writing into COR and CSR registers as well as

attribute memory space.

90 Interrupt INTR0 O24 ISA - Active high interrupt signal. The interrupt

line selection is determined by the value of

INT SEL1-0 bits in the Configuration Register.

This interrupt is tri-stated when not selected.

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