Si4432
Preliminary Rev. 0.4 5
LIST OF FIGURES
Figure 1. +20 dBm Application with Antenna Diversity and FHSS............................................17
Figure 2. SPI Timing..................................................................................................................19
Figure 3. SPI Timing—READ Mode ..........................................................................................20
Figure 4. SPI Timing—Burst Write Mode ..................................................................................20
Figure 5. SPI Timing—Burst Read Mode .................................................................................. 20
Figure 6. State Machine Diagram..............................................................................................21
Figure 7. TX Timing...................................................................................................................25
Figure 8. RX Timing ..................................................................................................................26
Figure 9. Frequency Deviation ..................................................................................................30
Figure 10. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................31
Figure 11. FSK vs GFSK Spectrums.........................................................................................34
Figure 12. Direct Synchronous Mode Example......................................................................... 36
Figure 13. Direct Asynchronous Mode Example ....................................................................... 36
Figure 14. FIFO Mode Example ................................................................................................37
Figure 15. PLL Synthesizer Block Diagram...............................................................................39
Figure 16. FIFO Thresholds ......................................................................................................42
Figure 17. Packet Structure.......................................................................................................43
Figure 18. Multiple Packets in TX Packet Handler .................................................................... 44
Figure 19. Required RX Packet Structure with Packet Handler Disabled .................................44
Figure 20. Multiple Packets in RX Packet Handler....................................................................44
Figure 21. Multiple Packets in RX with CRC or Header Error ...................................................45
Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC ..............................47
Figure 23. POR Glitch Parameters............................................................................................55
Figure 24. General Purpose ADC Architecture .........................................................................57
Figure 25. ADC Differential Input Example—Bridge Sensor .....................................................58
Figure 26. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................59
Figure 27. Temperature Ranges using ADC8 ...........................................................................61
Figure 28. WUT Interrupt and WUT Operation..........................................................................64
Figure 29. Low Duty Cycle Mode ..............................................................................................65
Figure 30. GPIO Usage Examples............................................................................................67
Figure 31. RSSI Value vs. Input Power.....................................................................................69
Figure 32. Split RF I/Os with Separated TX and RX Connectors—Schematic .........................70
Figure 33. Common TX/RX Connector with RF Switch—Schematic ........................................72
Figure 34. Antenna Diversity Reference Design—Schematic...................................................74
Figure 35. Sensitivity vs. Data Rate ..........................................................................................76
Figure 36. Receiver Selectivity..................................................................................................77
Figure 37. TX Output Power vs. VDD Voltage ..........................................................................78
Figure 38. TX Output Power vs Temperature ...........................................................................78
Figure 39. TX Modulation (40 kbps, 20 kHz Deviation).............................................................79
Figure 40. TX Unmodulated Spectrum (917 MHz) ....................................................................79
Figure 41. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) .................80
Figure 42. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ...........................80
Figure 43. Synthesizer Phase Noise (VCOCURR = 11) ...........................................................81
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