Sensoray 526 Manuel utilisateur

PC/104 Multifunction I/O Board

Hardware Manual

Model 526 | Rev B | February 2009

Table of Contents

TABLE OF CONTENTS......................................................................................................... 2

LIMITED WARRANTY.......................................................................................................... 4

SPECIAL HANDLING INSTRUCTIONS .................................................................................... 4

INTRODUCTION................................................................................................................. 5

PROGRAMMABLE COUNTERS............................................................................................... 7

Input S gnals................................................................................................................. 7

Captured Events............................................................................................................ 8

Output S gnals .............................................................................................................. 8

Counter Preload ............................................................................................................ 8

Output Reg ster............................................................................................................. 9

Examples of Counter Appl cat ons.................................................................................... 9

One-shot (software tr gger).......................................................................................... 9

One-shot (hardware tr gger)....................................................................................... 10

Pulse W dth Modulat on.............................................................................................. 10

INTERRUPT TIMER........................................................................................................... 11

WATCHDOG TIMER .......................................................................................................... 11

Watchdog enable/d sable ............................................................................................. 12

Sol d-sate relay control................................................................................................. 12

D/A CONVERTER.............................................................................................................. 13

Cal brat on .................................................................................................................. 13

A/D CONVERTER.............................................................................................................. 13

Cal brat on .................................................................................................................. 13

DIGITAL I/O.................................................................................................................... 15

INTERRUPTS ................................................................................................................... 15

CALIBRATION EEPROM..................................................................................................... 16

CONFIGURATION JUMPERS............................................................................................... 17

CONNECTORS.................................................................................................................. 17

Analog connector (J3) .................................................................................................. 17

D g tal connector (J5)................................................................................................... 18

REGISTERS ..................................................................................................................... 19

Reg ster Map............................................................................................................... 19

T mer Control Reg ster ................................................................................................ 20

Watchdog T mer Control Reg ster .................................................................................. 20

DAC Control Reg ster ................................................................................................... 21

ADC Control Reg ster ................................................................................................... 22

DAC/ADC Data Reg ster................................................................................................ 22

D g tal I/O Control Reg ster........................................................................................... 23

Interrupt Enable Reg ster ............................................................................................. 24

Interrupt Status Reg ster .............................................................................................. 24

M scellaneous Reg ster ................................................................................................. 25

Counter Preload/Data Reg ster low word ........................................................................ 25

Counter Preload/Data Reg ster h gh word....................................................................... 25

Counter Mode Reg ster................................................................................................. 26

Counter Control/Status Reg ster .................................................................................... 27

EEPROM Data Reg ster................................................................................................. 28

EEPROM Command/Status Reg ster ............................................................................... 28

SPECIFICATIONS ............................................................................................................. 29

Limited warranty

Sensoray Company, Incorporated (Sensoray) warrants the hardware to be free from defects n

mater al and workmansh p and perform to appl cable publ shed Sensoray spec f cat ons for two

years from the date of sh pment to purchaser. Sensoray w ll, at ts opt on, repa r or replace

equ pment that proves to be defect ve dur ng the warranty per od. Th s warranty ncludes parts

and labor.

The warranty prov ded here n does not cover equ pment subjected to abuse, m suse, acc dent,

alterat on, neglect, or unauthor zed repa r or nstallat on. Sensoray shall have the r ght of f nal

determ nat on as to the ex stence and cause of defect.

As for tems repa red or replaced under warranty, the warranty shall cont nue n effect for the

rema nder of the or g nal warranty per od, or for n nety days follow ng date of sh pment by

Sensoray of the repa red or replaced part, wh chever per od s longer.

A Return Mater al Author zat on (RMA) number must be obta ned from the factory and clearly

marked on the outs de of the package before any equ pment w ll be accepted for warranty work.

Sensoray w ll pay the sh pp ng costs of return ng to the owner parts that are covered by

warranty. A restock ng charge of 25% of the product purchase pr ce, or $105, wh chever s less,

w ll be charged for return ng a product to stock.

Sensoray bel eves that the nformat on n th s manual s accurate. The document has been

carefully rev ewed for techn cal accuracy. In the event that techn cal or typograph cal errors ex st,

Sensoray reserves the r ght to make changes to subsequent ed t ons of th s document w thout

pr or not ce to holders of th s ed t on. The reader should consult Sensoray f errors are suspected.

In no event shall Sensoray be l able for any damages ar s ng out of or related to th s document or

the nformat on conta ned n t.

EXCEPT AS SPECIFIED HEREIN, SENSORAY MAKES NO WARRANTIES, EXPRESS

OR IMPLIED, AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF

MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. CUSTOMER’S

RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE

PART OF SENSORAY SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID

BY THE CUSTOMER. SENSORAY WILL NOT BE LIABLE FOR DAMAGES

RESULTING FROM LOSS OF DATA, PROFITS, USE OF PRODUCTS, OR

INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE

POSSIBILITY THEREOF.

Th rd party brands, names and trademarks are the property of the r respect ve owners.

Special handling instructions

The c rcu t board conta ns CMOS c rcu try that s sens t ve to Electrostat c D scharge (ESD).

Spec al care should be taken n handl ng, transport ng, and nstall ng c rcu t board to prevent ESD

damage to the board. In part cular:

•Do not remove the c rcu t board from ts protect ve ant -stat c bag unt l you are ready to

nstall the board nto the enclosure.

•Handle the c rcu t board only at grounded, ESD protected stat ons.

•Remove power from the equ pment before nstall ng or remov ng the c rcu t board.

Introduction

Model 526 s a PC/104 mult funct onal I/O board w th the follow ng features:

•Four 24-b t programmable counters. Inputs could be dr ven from ncremental encoders ( n

1x, 2x, or 4x modes) or any d g tal s gnal. Inputs accept d fferent al (RS-422) or standard

TTL/CMOS s ngle-ended s gnals. The counters can also count nternal clock (27 or 13.5 MHz).

•E ght d g tal I/O channels conf gurable as nputs or outputs ( n groups of 4) and capable of

generat ng nterrupts.

•4-channel 16-b t D/A converter (±10 V).

•8-channel (mult plexed) d fferent al 16-b t A/D converter (±10 V).

•Programmable nterrupt t mer.

•Watchdog t mer w th conf gurable t meout and output.

•EEPROM for cal brat on data storage.

•Flex ble address and nterrupt l ne conf gurat on.

•Requ res one power supply (+5V).

Model 526 s controlled through a set of 27 reg sters mapped nto I/O space. The base address of

the board s selected w th jumpers from a range of 0x0000 to 0xFFC0. The board s sh pped w th

the base address set to 0x2C0. All reg ster accesses are 16 b t; 1 byte and odd address accesses

are not supported. The total I/O space cla med by the board s 0x40 (64) bytes.

Model 526 can generate nterrupts on var ous programmable cond t ons. The nterrupt l ne used

by the board s selected w th jumpers from the follow ng IRQ values: 3, 4, 5, 6, 7, 9, 10, 11, 12,

14 and 15. The board s sh pped w th the nterrupt set to IRQ3.

F g.1. Model 526 board outl ne.

Programmable Counters

Model 526 conta ns 4 dent cal 24-b t up/down counters w th enable and preload. The block

d agram of one of the counters s shown on F g.2.

"1"

ECAP

SOFTWARE LOAD

PRELOAD BUFFER 0

UP/DOWN

POWER-ON RESET

CLKB

INTERNAL

INDEX

"1"

CLK

D Q

DATA BUS

CLKA

SOFTWARE RESET

RTGL

"1"

ICAP-

ENABLE

CLK

D Q

CLK

D Q

COUNTER CORE

LOAD

ROLLOVER

LATCH

RTGL

INDEX^

ROLLOVER

CLOCK

RCAP

CLK

D Q

INDEXv

COUT

CLOCK MUX/

QUADRATURE

DETECTOR

PRELOAD BUFFER 1

RESET

INTERNAL/2

CLK

D Q

"1"

ICAP+

ERROR

DATA BUS

F g.2. Counter s mpl f ed block d agram.

See the descr pt on of Counter Mode reg ster and Counter Control/Status reg ster n the

Registers sect on for the mplementat on spec f cs.

Input Signals

The counter accepts the follow ng nput s gnals (connector J5):

•CLKA – phase A of the encoder, or any clock s gnal n normal mode;

•CLKB – phase B of the encoder;

•INDEX – ndex s gnal of the encoder, or any d g tal s gnal;

•CE – external count enable.

S gnals CLKA, CLKB and INDEX could be e ther d fferent al (RS-422), or s ngle-ended. In case of a

s ngle-ended s gnal the “+” nput has to be used.

The clock source can be selected through the software. In quadrature mode the poss ble clock

sources are:

•quadrature x1 (CLKA↑ count ng up, CLKA↓ count ng down);

•quadrature x2 (both edges of CLKA);

•quadrature x4 (both edges of both CLKA and CLKB);

In normal mode the clock sources are:

•CLKA↑;

•CLKA↓;

•Internal clock (27 MHz);

•Internal clock d v ded by 2 (13.5 MHz).

Count d rect on (up or down) s set through the software (normal mode) or determ ned from

CLKA-CLKB phase relat onsh p (quadrature mode).

Count s enabled e ther through the software, or w th the external s gnal. Poss ble sources of

Count Enable s gnal are:

•CEN;

•INDEX;

•INDEX↑ to INDEX↓ (count does not start unt l the r s ng edge of INDEX s gnal);

•NOT RCAP (see the descr pt on of RCAP s gnal below).

The polar ty of Count Enable s gnal can be nverted through the software.

Captured Events

The counter detects or generates the follow ng “short” events:

•RO – rollover, counter overflow (when count ng up) or underflow (when count ng down);

•INDEX↑ - r s ng edge of INDEX s gnal;

•INDEX↓ - fall ng edge of INDEX s gnal;

•ERROR – llegal quadrature state trans t on.

“Short” events can generate nterrupts, f enabled.

To fac l tate rel able detect on by the software, the “short” events are captured (see F g.2), thus

generat ng correspond ng captured events:

•RCAP – captured RO s gnal;

•ICAP+ - captured r s ng edge of INDEX s gnal;

•ICAP- - captured fall ng edge of INDEX s gnal;

•ECAP – captured ERROR s gnal.

Captured events status can be read and reset through the Control/Status Reg ster.

Add t onally, RO generates RTGL – a s gnal wh ch toggles each t me rollover s generated.

Output Signals

The follow ng s gnals can be routed to the counter output s gnal (COUT):

•RCAP;

•RTGL.

The polar ty of COUT s gnal can be nverted through the software.

Counter Preload

Each counter has 2 preload reg sters access ble nd v dually through the software, PR0 and PR1.

The counter s loaded from a preload reg ster under software control (from PR0), or

automat cally. The preload reg ster from wh ch the counter s loaded n automat c mode s

determ ned by the state of the RTGL s gnal: PR0 when RTGL s low, PR1 when RTGL s h gh. The

autoload occurs under a programmable comb nat on of the follow ng cond t ons:

•INDEX↑ - r s ng edge of INDEX s gnal;

•INDEX↓ - fall ng edge of INDEX s gnal;

•RO – rollover.

See appl cat on examples below for the explanat on of preload reg sters usage.

The preload reg sters are 24 b ts long, so they can not be wr tten to w th one operat on. In order

to prevent the s tuat on when the counter s loaded w th ncomplete data, an ntermed ate buffer

holds the h gh word of a preload reg ster unt l the data s wr tten to the low word, so that both

h gh and low words are wr tten to the preload reg ster s multaneously. Thus the h gh word has to

be always wr tten f rst.

Output Register

Counter output data (24-b t) requ res 2 read accesses to be read out. To ensure that all b ts of

the read ng correspond to the same nstant each counter has an output reg ster. The data can be

latched nto the output reg ster e ther by a read access to the low word of Counter Data reg ster,

or by a hardware event, depend ng on the state of “Output reg ster latch control” b t of the

Counter Mode reg ster. The hardware event that can latch the counter data s a log cal OR of any

of the follow ng: INDEX r s ng edge, INDEX fall ng edge, nterrupt t mer exp rat on.

Latch ng the data nto the output reg ster does not nterrupt the count. Latch ng on read access

occurs on the access to the low word, so n case “Latch on read” mode s selected the low word

has to be always read f rst.

Examples of Counter Applications

All the follow ng examples assume the use of counter 0. The pseudocode funct on

Reg sterWr te(address, data) has a mean ng of wr t ng a 2-byte word

data

to I/O address

(

base+address

), where

base

s the base I/O address of the board.

One-shot (software trigger

In th s mode the counter clock source s set to nternal, so the length of the generated pulse

s expressed n un ts of 1/27 MHz ≈ 37 ns. Assum ng the des red pos t ve go ng pulse length s

3 ms the counter has to be loaded w th the value of 3 ms x 27 MHz = 81,000 = 0x13C68.

The Count Enable s set to NOT RCAP, the counter output (COUT) to RCAP w th COUT polar ty

nverted.

Step 1. Load the preload reg ster PR0 w th 0x13C68. F rst, set the Counter Mode reg ster.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0

X PR0 X Soft

count

d rect on

control

Count

d rect on:

down

Clock

source:

nternal

Count

enable:

hardware

NOT

RCAP

Auto load:

d sable

Polar ty:

nverted

Out:

RCAP

// select PR0 as a target for Preload register access

// set operating mode, don’t enable count yet

RegisterWrite (0x16, 0x1D62); //load Counter Mode register

RegisterWrite (0x14, 0x0001); //load Preload Register high word

RegisterWrite (0x12, 0x3C68); //load Preload Register low word

Step 2. Reset the counter (to clear RTGL), load the counter from Preload Reg ster 0.

RegisterWrite (0x18, 0x8000); //reset the counter

RegisterWrite (0x18, 0x4000); //load the counter from PR0

Step 3. Reset RCAP (f res one-shot).

RegisterWrite (0x18, 0x8);

One-shot (hardware trigger

The follow ng example shows how to f re the one-shot on the pos t ve edge of external

tr gger. The tr gger s gnal s connected to the INDEX nput of the counter.

Step 1. Load both preload reg sters PR0 and PR1 w th 0x13C68. F rst, set the Counter Mode

reg ster.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0

X PR0 X Soft

count

d rect on

control

Count

d rect on:

down

Clock

source:

nternal

Count

enable:

hardware

NOT

RCAP

Auto load and

reset RCAP:

INDEX↑

Polar ty:

nverted

Out:

RCAP

// select PR0 as a target for Preload register access

// do not enable autoload (bit 4) yet

RegisterWrite (0x16, 0x1D62); //load Counter Mode register

RegisterWrite (0x14, 0x0001); //load Preload Register 0 high word

RegisterWrite (0x12, 0x3C68); //load Preload Register 0 low word

// select PR1 as a target for Preload register access

RegisterWrite (0x16, 0x5D62); //load Counter Mode register

RegisterWrite (0x14, 0x0001); //load Preload Register 1 high word

RegisterWrite (0x12, 0x3C68); //load Preload Register 1 low word

Step 2.

// enable autoload

RegisterWrite (0x16, 0x3D72); //load Counter Mode register

Pulse Width Modulation

Let’s assume the follow ng requ rements:

Per od = 10 ms; “h gh” state = 2 ms; “low” state = 8 ms. Then the “h gh” length n per ods of

the 27 MHz clock s 2 ms x 27 MHz = 54000 = 0xD2F0, the “low” length s 8 ms x 27 MHz =

216000 = 0x34BC0.

Step 1. Load Preload Reg ster 0.

// select PR0 as a target for Preload register access, load PR0

RegisterWrite (0x16, 0x1C85); //load Counter Mode register

RegisterWrite (0x14, 0x0003); //load Preload Register 0 high word

RegisterWrite (0x12, 0x4BC0); //load Preload Register 0 low word

Step 2. Load Preload Reg ster 1.

// select PR1 as a target for Preload register access, load PR1

RegisterWrite (0x16, 0x5C85); //load Counter Mode register

RegisterWrite (0x14, 0x0000); //load Preload Register 0 high word

RegisterWrite (0x12, 0xD2F0); //load Preload Register 0 low word

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