Philips TDA8767 Manuel utilisateur

DATA SHEET

Preliminary speciﬁcation

Supersedes data of 1997 Jun 27

File under Integrated Circuits, IC02

1999 Feb 16

INTEGRATED CIRCUITS

TDA8767

12-bit high-speed Analog-to-Digital

Converter (ADC)

1999 Feb 16 2

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

FEATURES

•12-bit resolution

•Sampling rate up to 30 MHz

•−3 dB bandwidth of 18 MHz

•No missing codes guaranteed

•5 V power supplies

•Binary or two’s complement CMOS outputs

•In-range CMOS output

•TTL/CMOS compatible static digital inputs

•3 to 5 V CMOS digital outputs

•TTL compatible clock input

•Power dissipation 335 mW (typ.)

•Low analog input capacitance (typ. 2 pF), no buffer

amplifier required

•No external sample-and-hold circuit required

•Differential or single analog Input

•External amplitude range control

•Voltage controlled regulator included.

APPLICATIONS

•High-speed analog-to-digital conversion for:

– Video signal digitizing

– High Definition TV (HDTV)

– Imaging (camera, scanner)

– Medical imaging

– Telecommunication

– Base-station receiver.

GENERAL DESCRIPTION

The TDA8767 is a bipolar 12-bit Analog-to-Digital

Converter (ADC) for imaging or other applications.

It converts the analog input signal into 12-bit binary coded

digital words at a maximum sampling rate of 30 MHz.

All digital inputs and outputs are CMOS compatible.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCCA analog supply voltage 4.75 5.0 5.25 V

VCCD digital supply voltage 4.75 5.0 5.25 V

VCCO output supply voltage 3.0 3.3 5.25 V

ICCA analog supply current −40 tbf mA

ICCD digital supply current −22 tbf mA

ICCO output supply current fclk = 4 MHz; fi= 400 kHz −3.2 tbf mA

ILE integral non-linearity fclk = 4 MHz; fi= 400 kHz −±3.0 ±4.0 LSB

DLE differential non-linearity fclk = 4 MHz; fi= 400 kHz;

no missing codes −±0.6 ±1 LSB

fclk(max) maximum clock frequency

TDA8767H/1 10 −−MHz

TDA8767H/2 20 −−MHz

TDA8767H/3 30 −−MHz

Ptot total power dissipation −335 −mW

1999 Feb 16 3

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE

NUMBER PACKAGE SAMPLING

FREQUENCY (MHz)

NAME DESCRIPTION VERSION

TDA8767H/1 QFP44 plastic quad ﬂat package; 44 leads

(lead length 1.3 mm); body 10 ×10 ×1.75 mm SOT307-2 10

TDA8767H/2 20

TDA8767H/3 30

Fig.1 Block diagram.

handbook, full pagewidth

MBH142

D11 MSB

data outputs

D1022

D923

D824

D725

D626

D527

Vref

VID230

D131

D0 LSB

VCCO

CMOS

OUTPUTS

LATCHES

ANALOG-TO-DIGITAL

CONVERTER

CLOCK DRIVER

VCCD2

VCCD1

VCCA4

VCCA3

VCCA2

VCCA1

CLK

CMOS

OUTPUT

OGND

IN-RANGE

LATCH

OETC

AMP

sample-

and-hold

TDA8767

DGND2

DGND1

digital ground

AGND4

AGND3

AGND2

AGND1

analog ground

1999 Feb 16 4

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected

VCCA1 2 analog supply voltage 1 (+5 V)

VCCA3 3 analog supply voltage 3 (+5 V)

AGND3 4 analog ground 3

n.c. 5 not connected

n.c. 6 not connected

n.c. 7 not connected

n.c. 8 not connected

VCCA2 9 analog supply voltage 2 (+5 V)

AGND2 10 analog ground 2

Vref 11 reference voltage

n.c. 12 not connected

n.c. 13 not connected

n.c. 14 not connected

VCCD2 15 digital supply voltage 2 (+5 V)

n.c. 16 not connected

DGND2 17 digital ground 2

TC 18 output two’s complement

OE 19 output enable input

(CMOS level; active LOW)

IR 20 in-range output

D11 21 data output; bit 11 (MSB)

D10 22 data output; bit 10

D9 23 data output; bit 9

D8 24 data output; bit 8

D7 25 data output; bit 7

D6 26 data output; bit 6

D5 27 data output; bit 5

D4 28 data output; bit 4

D3 29 data output; bit 3

D2 30 data output; bit 2

D1 31 data output; bit 1

D0 32 data output; bit 0 (LSB)

VCCO 33 output supply voltage (3 to 5.25 V)

OGND 34 output ground

n.c. 35 not connected

CLK 36 clock input

VCCD1 37 digital supply voltage 1 (+5 V)

DGND1 38 digital ground 1

SH 39 sample-and-hold enable input

(CMOS level; active HIGH)

AGND4 40 analog ground 4

VCCA4 41 analog supply voltage 4 (+5 V)

VI42 complementary analog input voltage

VI43 analog input voltage

AGND1 44 analog ground 1

SYMBOL PIN DESCRIPTION

1999 Feb 16 5

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

Fig.2 Pin configuration.

handbook, full pagewidth

TDA8767

MBH143

n.c.

VCCA1

VCCA3

VCCA2

Vref

AGND3

AGND2

n.c.

D11

D10

DGND2

VCCD2

OGND

DGND1

AGND4

AGND1

VCCD1

VCCA4

n.c.

VCCO

CLK

1999 Feb 16 6

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided that the supply

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VCCA analog supply voltage note 1 −0.3 +7.0 V

VCCD digital supply voltage note 1 −0.3 +7.0 V

VCCO output supply voltage note 1 −0.3 +7.0 V

∆VCC supply voltage difference

VCCA −VCCD −1.0 +1.0 V

VCCO −VCCD −1.0 +4.0 V

VCCA −VCCO −1.0 +4.0 V

VIinput voltage referenced to AGND 0.3 VCCA V

Vi(p-p) input voltage for differential clock

drive (peak-to-peak value) −VCCD V

IOoutput current −10 mA

Tstg storage temperature −55 +150 °C

Tamb operating ambient temperature 0 70 °C

Tjjunction temperature −+150 °C

SYMBOL PARAMETER VALUE (TYP.) UNIT

Rth j-a thermal resistance from junction to ambient in free air 75 K/W

1999 Feb 16 7

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

CHARACTERISTICS

VCCA =V

2to V44, V9to V10, V3to V4and V41 to V40 = 4.75 to 5.25 V; VCCD =V

37 to V38 and V15 to V17 = 4.75 to 5.25 V;

VCCO =V

33 to V34 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at

VCCA =V

CCD = 5 V and VCCO = 3.3 V; Vi(p-p) −Vi(p-p) = 2.0 V; CL= 15 pF and Tamb =25°C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

VCCA analog supply voltage 4.75 5.0 5.25 V

VCCD digital supply voltage 4.75 5.0 5.25 V

VCCO output supply voltage 3.0 3.3 5.25 V

ICCA analog supply current −40 tbf mA

ICCD digital supply current −22 tbf mA

ICCO output supply current fclk = 20 MHz; fi= 4.43 MHz −12 tbf mA

Inputs

CLK (REFERENCED TO DGND)

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2.0 −VCCD V

IIL LOW-level input current Vclk = 0.3VCCD −400 −−µA

IH HIGH-level input current Vclk = 0.7VCCD −−100 µA

Vclk =V

CCD −−300 µA

Ziinput impedance fclk = 30 MHz −2−kΩ

Ciinput capacitance fclk = 30 MHz −2−pF

TC; SH AND OE (REFERENCED TO DGND); see Tables 3 and 4

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2.0 −VCCD V

IIL LOW-level input current VIL = 0.3VCCD −400 −−µA

IH HIGH-level input current VIH = 0.7VCCD −−20 µA

VIAND VI(REFERENCED TO AGND; see Tables 1 AND 2); Vref =V

CCA −2V

IL LOW-level input current Vi= Vi−10 −µA

IH HIGH-level input current Vi= Vi−10 −µA

iinput impedance fi= 4.43 MHz −10 −kΩ

Ciinput capacitance fi= 4.43 MHz −2−pF

Vios(d) input offset voltage in

differential mode VI= VI; output code 2047

VCCA = 5 V tbf 2.5 tbf V

VCCA = 4.75 V tbf 2.25 tbf V

VCCA = 5.25 V tbf 2.75 tbf V

Vios(s) input offset voltage in single

mode VI=V

ios(s); output

code 2047

VCCA = 5 V tbf 2.5 tbf V

VCCA = 4.75 V tbf 2.25 tbf V

VCCA = 5.25 V tbf 2.75 tbf V

1999 Feb 16 8

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

Voltage controlled regulator input Vref (referenced to VCCA)

Vref(FS) full scale ﬁxed voltage VCCA =5V −3.175 −V

Vi(p-p) −Vi(p-p) input voltage amplitude

(peak-to-peak value) differential mode −2.0 −V

single mode; Vi= 2.5 V −2.0 −V

Iref input current at Vref −10 −µA

Outputs (referenced to DGND)

DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)

VOL LOW-level output voltage IOL = 2 mA 0 −0.5 V

VOH HIGH-level output voltage IOH =−0.4 mA VCCO −0.5 −VCCD V

IOoutput current in 3-state 0.5 V < VO<V

CCO −20 −+20 µA

Switching characteristics

CLOCK FREQUENCY fclk (see Fig.3)

fclk(min) minimum clock frequency SH = HIGH −−1 MHz

SH = LOW −−1 kHz

fclk(max) maximum clock frequency

TDA8767H/1 10 −−MHz

TDA8767H/2 20 −−MHz

TDA8767H/3 30 −−MHz

tCPH clock pulse width HIGH 8.5 −−ns

tCPL clock pulse width LOW 8.5 −−ns

Analog signal processing; 50% clock duty factor; Vi−Vi= 2.0 V; Vref =V

CCA −2V;see Table 1

LINEARITY

ILE integral non-linearity fclk = 4 MHz; ramp input −±3.0 ±4.0 LSB

DLE differential non-linearity fclk = 4 MHz; ramp input;

no missing codes −±0.6 ±1 LSB

OFER offset error VCCA =V

CCD =V

CCO =5V;

amb =25°C; Vi= Vi; output

code = 2047

tbf −tbf LSB

GER gain error amplitude; spread

from device to device VCCA =V

CCD =V

CCO =5V;

amb =25°C; Vi−Vi=2.0 V tbf −tbf LSB

BANDWIDTH (fclk = 30 MHz); note 1

B analog bandwidth −1dB −9−MHz

−3dB −18 −MHz

tSTLH analog input settling time

LOW-to-HIGH transition full scale square wave;

note 3 −tbf −ns

tSTHL analog input settling time

HICH-to-LOW transition full scale square wave;

note 3 −tbf −ns

HARMONICS

THD total harmonic distortion fclk = 30 MHz; fi= 4.43 MHz;

note 2 −−64 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Feb 16 9

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

Notes to the characteristics

1. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,

the input being a full-scale sine wave.

2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).

4. Output data acquisition: the output data is available after the maximum delay of td.

SIGNAL-TO-NOISE RATIO

S/N signal-to-noise ratio without harmonics;

fclk = 30 MHz; fi= 4.43 MHz −61 −dB

Timing (CL= 15 pF); note 4; see Fig.3

tds sampling delay time −−2ns

houtput hold time 8 −−ns

tdoutput delay time VCCO = 4.75 V −12 15 ns

VCCO = 3.15 V 15 18 ns

3-state output delay times; see Fig.4

tdZH enable HIGH −14 18 ns

tdZL enable LOW −16 20 ns

tdHZ disable HIGH −16 20 ns

tdLZ disable LOW −14 18 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

THD 20log F

(2nd)2(3rd)2(4th)2(5th)2(6th)2

++++

---------------------------------------------------------------------------------------------------------------=

1999 Feb 16 10

Philips Semiconductors Preliminary speciﬁcation

12-bit high-speed Analog-to-Digital

Converter (ADC) TDA8767

Table 1 Output coding with differential inputs (typical values to AGND); VI(p-p) −VI(p-p) =2.0 V; Vref =V

CCA −2V

Table 2 Output coding with single input (typical values to AGND); VFS = 2.0 V (p-p); Vref =V

CCA −2V

Table 3 Mode selection

Note

1. Where: X = don’t care.

Table 4 Sample-and-hold selection

CODE VIVIIR BINARY OUTPUTS TWO’S COMPLEMENT

OUTPUTS

D11 to D0 D11 to D0

underﬂow <2.0 >3.0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 2.0 3.0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00

1−−1 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 1

↓−−↓ ↓ ↓

2047 2.5 2.5 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−−↓ ↓ ↓

4094 −−1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0

4095 3.0 2.0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

overﬂow >3.0 <2.0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

CODE VIIR BINARY OUTPUTS TWO’S COMPLEMENT

OUTPUTS

D11 to D0 D11 to D0

underﬂow <1.5 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

0 1.5 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00

1−1 0 0 0 0 0 0 0 0 0 0 01 1 0 0 0 0 0 0 0 0 0 0 1

↓−↓ ↓ ↓

2047 2.5 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

↓−↓ ↓ ↓

4094 −1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0

4095 3.5 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

overﬂow >3.5 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

TC OE D0 to D11 and IR

0 0 binary; active

1 0 two’s complement; active

X(1) 1 high impedance

SH SAMPLE-AND-HOLD

1 active

0 inactive; tracking mode

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