Lattice Semiconductor CrossLink-NX Manuel utilisateur

CrossLink-NX PCIe Bridge Board

Multifunction Demo

User Guide

FPGA-UG-02150-1.0

February 2022

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-UG-02150-1.0

Disclaimers

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its

products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.

Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited

testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice

products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a

situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is

proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at

any time without notice.

 CrossLink-NX PCIe Bridge Board Multifunction Demo 
 User Guide 
 
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-UG-02150-1.0 3 
Contents 
Acronyms in This Document.................................................................................................................................................6 
Introduction..................................................................................................................................................................7 
1. Learning Objectives.............................................................................................................................................7 
Hardware and Software Requirements........................................................................................................................8 
1. Hardware Requirements.....................................................................................................................................8 
2. Software Requirements ......................................................................................................................................8 
Setting Up the Demo ....................................................................................................................................................9 
1. Hardware Setup ..................................................................................................................................................9 
1.1. Jumper Configuration.....................................................................................................................................9 
1.2. Programming the FPGA................................................................................................................................10 
1.3. Status LED.....................................................................................................................................................13 
2. Software Setup..................................................................................................................................................14 
2.1. Software Setup and Installation for Windows .............................................................................................14 
2.2. Software Setup for Linux..............................................................................................................................29 
Demo Design Overview ..............................................................................................................................................32 
1. Theory of Operation..........................................................................................................................................32 
2. Design Overview ...............................................................................................................................................33 
2.1. GUI Application ............................................................................................................................................33 
2.2. Device Drivers...............................................................................................................................................33 
2.3. Device Hardware (FPGA Design) ..................................................................................................................34 
Application Overview .................................................................................................................................................35 
1. Running the PCI Express Demo Application......................................................................................................35 
2. Using the PCI Express Demo Application User Interface...................................................................................36 
2.1. Functionality Test Tab ..................................................................................................................................36 
2.2. GPIO .............................................................................................................................................................36 
2.3. I2C.................................................................................................................................................................37 
2.4. MDIO ............................................................................................................................................................44 
Importing and Building the FPGA Demonstration......................................................................................................47 
1. Hardware Directory Structure...........................................................................................................................47 
2. Building Lattice Radiant Project ........................................................................................................................47 
Troubleshooting .........................................................................................................................................................48 
1. SPI Flash Update................................................................................................................................................48 
2. Driver Installation and User Interface Launch for Windows.............................................................................49 
2.1. Problem in Driver Installation ......................................................................................................................49 
2.2. Problem with Launching User Interface.......................................................................................................49 
3. Driver Installation User Interface Launch for Linux...........................................................................................50 
3.1. Problem in Driver Loading............................................................................................................................50 
3.2. Problem with User Interface Launching.......................................................................................................51 
Technical Support Assistance .............................................................................................................................................52 
Revision History..................................................................................................................................................................53 
 

CrossLink-NX PCIe Bridge Board Multifunction Demo 
User Guide 
 
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
4 FPGA-UG-02150-1.0 
Figures 
Figure 3.1. CrossLink-NX PCIe Bridge Board Jumper Location..............................................................................................9 
Figure 3.2. CrossLink-NX PCIe Bridge Board Connection....................................................................................................10 
Figure 3.3. Creating a New Project from a Scan .................................................................................................................10 
Figure 3.4. Radiant Programmer Window ..........................................................................................................................11 
Figure 3.5. FPGA Device Settings ........................................................................................................................................11 
Figure 3.6. Device Properties Window for SPI Flash Programming....................................................................................12 
Figure 3.7. Programmer Menu Bar.....................................................................................................................................12 
Figure 3.8. Programmer Output Window...........................................................................................................................12 
Figure 3.9. Status LED .........................................................................................................................................................13 
Figure 3.10. Running Disable Integrity Checks Command..................................................................................................14 
Figure 3.11. Running Test Sign On Command.....................................................................................................................14 
Figure 3.12. Troubleshoot Option.......................................................................................................................................15 
Figure 3.13. Advanced Options...........................................................................................................................................15 
Figure 3.14. Select Startup Settings....................................................................................................................................16 
Figure 3.15. Restarting Windows........................................................................................................................................16 
Figure 3.16. Welcome Page ................................................................................................................................................17 
Figure 3.17. Destination Folder Page..................................................................................................................................18 
Figure 3.18. Summary Page ................................................................................................................................................18 
Figure 3.19. Application Installed .......................................................................................................................................19 
Figure 3.20. Device Configuration Prompt .........................................................................................................................19 
Figure 3.21. Device Driver Installation Wizard ...................................................................................................................20 
Figure 3.22. Windows Security in Driver Installation..........................................................................................................20 
Figure 3.23. Device Driver Installation Completed .............................................................................................................21 
Figure 3.24. Device Manager..............................................................................................................................................21 
Figure 3.25. Showing Device Properties .............................................................................................................................22 
Figure 3.26. Hardware IDs of MDIO Device ........................................................................................................................23 
Figure 3.27. Hardware IDs of I2C Device .............................................................................................................................23 
Figure 3.28. Hardware IDs of GPIO Device .........................................................................................................................24 
Figure 3.29. Update Driver Menu in Device Manager........................................................................................................25 
Figure 3.30. Update Driver Options....................................................................................................................................25 
Figure 3.31. Browse the Driver for Device..........................................................................................................................26 
Figure 3.32. Windows Security in Device Manager ............................................................................................................26 
Figure 3.33. Driver Installation Status Message .................................................................................................................27 
Figure 3.34. Multifunction Demo Device Name Displayed in Device Manager..................................................................27 
Figure 3.35. MDIO, I2C, and GPIO Device Drivers in Device Manager ................................................................................28 
Figure 4.1. Relationship of the Hardware and Software Components...............................................................................32 
Figure 4.2. PCIe Multifunction Demo SW Design................................................................................................................33 
Figure 4.3. PCIe Multifunction FPGA Design.......................................................................................................................34 
Figure 5.1. PCIe Test Application Device Info Tab ..............................................................................................................35 
Figure 5.2. Functionality Test Tab.......................................................................................................................................36 
Figure 5.3. GPIO Input Switch.............................................................................................................................................36 
Figure 5.4. GPIO Output LEDs. ............................................................................................................................................37 
Figure 5.5. I2C Bit-Rate Selection........................................................................................................................................37 
Figure 5.6. I2C Address Program.........................................................................................................................................37 
Figure 5.7. I2C Master Write...............................................................................................................................................37 
Figure 5.8. Single Write to an Arbitrary Address of IMX258-0AQH5 Camera.....................................................................38 
Figure 5.9. Sequential Write Starting from an Arbitrary Address of IMX258-0AQH5 Camera ...........................................38 
Figure 5.10. I2C Master Write Procedure...........................................................................................................................39 
Figure 5.11. I2C Master Read..............................................................................................................................................39 
Figure 5.12. Single Read from the Held Address of IMX258-0AQH5 camera .....................................................................40 
Figure 5.13. Sequential Read Starting from the Held Address of IMX258-0AQH5 Camera................................................40 
Figure 5.14. I2C Master Write to Write the Register Address.............................................................................................40 

 CrossLink-NX PCIe Bridge Board Multifunction Demo 
 User Guide 
 
© 2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-UG-02150-1.0 5 
Figure 5.15. I2C Master Read ..............................................................................................................................................41 
Figure 5.16. I2C Master Register Read ................................................................................................................................41 
Figure 5.17. Single Read from an Arbitrary Address of MX258-0AQH5 Camera................................................................41 
Figure 5.18. Sequential Read Starting from an Arbitrary Address of MX258-0AQH5 Camera...........................................41 
Figure 5.19. I2C Master Register Read ................................................................................................................................42 
Figure 5.20. I2C Master Register Read ................................................................................................................................42 
Figure 5.21. I2C Batch Mode Read/Write ...........................................................................................................................43 
Figure 5.22. MDIO Phy addr ...............................................................................................................................................44 
Figure 5.23. MDIO Configuration Register Read.................................................................................................................44 
Figure 5.24. MDIO Register Write.......................................................................................................................................44 
Figure 5.25. MDIO Configuration through File ...................................................................................................................45 
Figure 5.26. MDIO Configuration File Example...................................................................................................................45 
Figure 7.1. TCK Frequency Setting......................................................................................................................................48 
Figure 7.2. Port Selection....................................................................................................................................................48 
Figure 7.3. User Interface with No Device Driver ...............................................................................................................49 
Figure 7.4. lspci -vnm Output Image...................................................................................................................................50 
Figure 7.5. Content List of Demonstration/Linux Directory. ..............................................................................................51 
Figure 7.6. Content List of Software/Linux Directory .........................................................................................................51 
 
Tables 
Table 3.1. Jumper Configuration ..........................................................................................................................................9 
Table 3.2. Status LED Description.......................................................................................................................................13 
Table 5.1. Master Write Control Description......................................................................................................................38 
Table 5.2. Registers of MX258-0AQH5 CMOS Camera.......................................................................................................38 
Table 5.3. Master Register Read Control Description ........................................................................................................41 
Table 5.4. Transaction Log Control Description..................................................................................................................42 
Table 5.5. Batch Mode Control Description .......................................................................................................................43 
Table 5.6. MDIO Batch Mode Control Description.............................................................................................................45 
Table 5.7. MDIO Batch Mode Table Description ................................................................................................................45 
Table 5.8. MDIO Input File Description...............................................................................................................................46 
 

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

6 FPGA-UG-02150-1.0

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

BAR

Base Address Register

FDSOI

Fully Depleted Silicon on Insulator

FPGA

Field-Programmable Gate Array

LED

Light-emitting diode

MIPI

Mobile Industry Processor Interface

PCIe

PCI Express

PHY

Physical Layer

SPI

Serial Peripheral Interface

USB

Universal Serial Bus

I2C

Inter-integrated Circuit

MDIO

Management Data Input Output

GPIO

General Purpose Input Output

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-UG-02150-1.0 7

1. Introduction

This guide describes how to setup and run the PCIe Multifunction Demo on the CrossLink™-NX PCIe Bridge Board. The

CrossLink-NX Bridge Board features the CrossLink-NX FPGA in the 400-ball caBGA package (LIFCL-40-8BG400C), which is

built on the Lattice Nexus FPGA platform using low power 28 nm FDSOI technology. The board can expand the usability

of the CrossLink-NX FPGA with 2.5 Gbps Hardened MIPI D-PHY, 5 Gbps PCIe, 1.5 Gbps programmable I/O, DDR3, USB

3.0, Ethernet, and SGMII. Board resources such as jumpers, LED indicators, push buttons, and switches are available for

user-defined applications.

This guide familiarizes you with the process of setting up your PCI Express development environment. It is assumed

that you do not have any associated tools installed on your system.

The demo discussed in this document is the PCI Express Multifunction Demo.

1.1. Learning Objectives

After completing the steps in this guide, you will be able to perform the following:

Set up the CrossLink-NX PCIe Bridge Board and become familiar with its main features

Install all applicable development tools and PCI Express demos

Establish communication between the CrossLink-NX PCIe Bridge Board through the PCI Express link

Run the PCI Express Multifunction Demo which implements three separate PCI Express functions on a single

endpoint device. Each function allows you to control a different aspect of the CrossLink-NX PCIe Bridge Board.

Use what the demo teaches you about designing Lattice PCI Express solutions.

Modify and rebuild the PCI Express Multifunction Demo.

Become familiar with the software development tools and major design flow steps employed in this kit.

Use other existing documentation in conjunction with this guide.

This document assumes that you have already installed the Lattice Radiant™ design software. This document covers

some of the basic of function of Lattice Radiant software. If you would like to learn more about Lattice Radiant

software, refer to the Lattice Radiant software Help system.

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

8 FPGA-UG-02150-1.0

2. Hardware and Software Requirements

2.1. Hardware Requirements

To install the kit design and run the demo software, a computer with a PCI Express ×16, ×8, ×4, or ×1 slot is required.

The computer must also have a USB port and be able to run the Lattice Radiant Software. All other hardware and

drivers are included in the kit.

Mini-USB to USB-A cable for programming the bitstream

12 V Power Adapter

CrossLink-NX PCIe Bridge Board

2.2. Software Requirements

The following software is required to obtain the expected results for the procedures described in this guide:

Lattice Radiant Software 2.2 or later (available at the Lattice website Design Software and IP page).

CrossLink-NX Multifunction Demo for Windows 10 or Linux

Windows 10 or Ubuntu 18.04.6

Bit file for the CrossLink-NX board SPI Flash (LIFCL40_PCIe_MultiFunction.bit)

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-UG-02150-1.0 9

3. Setting Up the Demo

3.1. Hardware Setup

This section covers the steps in programming the demo to the SPI memory of the CrossLink-NX PCIe Bridge Board.

3.1.1. Jumper Configuration

Install the jumpers listed in Table 3.1. Note that J31, J32, and J33 are different from the default board configuration.

Table 3.1. Jumper Configuration

Jumper Checklist

Configuration

J11, J18

Connect pins 1 and 2

J7, J6, J13, J14

Connect pins 1 and 2

J31, J32, J33

Connect pins 1 and 2

J8, J9, J10, J15, J16, J19, J20, J21, J22, J23, J25, J26, J29, J30,

J34, J35, J36, J37, J38, J39, J42

These are current measurement headers and should be kept

Open.

J51

Connect pins 2 and 4

J48

Connect pins 2 and 3

J27

Connect pins 1 and 2

J45, J46

Connect pins 1 and 2

J17

Open

Figure 3.1 shows the location of the jumpers.

J48

J51 Current

Measurement

2-Pin Header J31, J32, J33

J17

J27

J45, J46

J11, J18 J7, J6, J13, J14

Functional Jumper

Current Measurment Jumper

Figure 3.1. CrossLink-NX PCIe Bridge Board Jumper Location

CrossLink-NX PCIe Bridge Board Multifunction Demo

User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 FPGA-UG-02150-1.0