Inteco RT-DAC/Zynq Manuel utilisateur

RT-DAC/Zynq

Rev 1.0

User’s Manual

Customised FPGA configuration

www.inteco.com.pl

INTECO

www.inteco.com.pl

RT-DAC/Zynq - User’s Manual

NOTES

INTECO

www.inteco.com.pl

RT-DAC/Zynq - User’s Manual

AFETY OF THE EQUIPMENT

The equipment, when used in accordance with the supplied instructions, within the parameter set for

its mechanical and electrical performance, should not cause any danger to health or safety if normal

engineering applications are observed.

If, in specific cases, circumstances exist in which a potential hazard may be brought about by careless

or improper use, these will be pointed out and the necessary precautions emphasised.

Some National Directives require to indicate on our equipment certain warnings that require attention

by the user. These have been indicated in the specified way by labels. The meaning of any labels that

may be fixed to the equipment instrument are explained in this manual.

Risk of electric shock

RODUCT IMPROVEMENTS

The Producer reserves a right to improve design and performance of the product without prior notice.

All major changes are incorporated into up-dated editions of manuals and this manual is believed to

be correct at the time of printing. However, some product changes which do not affect the capability of

the equipment, may not be included until it is necessary to incorporate other significant changes.

INTECO

www.inteco.com.pl

RT-DAC/Zynq - User’s Manual

LECTROMAGNETIC COMPATIBILITY

This equipment, when operated in accordance with the supplied documentation, does not cause

electromagnetic disturbance outside its immediate electromagnetic environment.

OPYRIGHT NOTICE

Inteco Sp. z o. o.

transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or

otherwise, without the prior permission of Inteco Ltd.

CKNOWLEDGEMENTS

Inteco Sp. z o. o. acknowledges all trademarks.

MICROSOFT, WINDOWS are registered trademarks of Microsoft Corporation.

MATLAB and Simulink are registered trademarks of MathWorks Inc.

INTECO

www.inteco.com.pl

RT-DAC/Zynq - User’s Manual

CONTENTS

INTRODUCTION AND GENERAL DESCRIPTION............................................................................ 6

1.1

ENERAL INFORMATION

................................................................................................................... 6

1.1

PECIFICATION

......................................................................................................................... 7

1.2

SYSTEM COMPONENTS

..................................................................................................................... 8

1.3

SOFTWARE INSTALLATION

................................................................................................................. 8

1.4

ETALINUX

...................................................................................................................................... 9

1.4.1. RTDACStartup...................................................................................................................... 9

1.4.2. FTP ..................................................................................................................................... 10

1.4.3. Telnet .................................................................................................................................. 10

1.4.4. Web Server ......................................................................................................................... 10

CONNECTOR PIN ASSIGNMENT............................................................................................... 11

STARTING PROCEDURE ................................................................................................................ 14

2.1

STARTING PROCEDURE

................................................................................................................... 14

RT-DAC/ZYNQ CONTROL WINDOW .............................................................................................. 15

3.1

D/A

AND

A/D................................................................................................................................. 15

3.1.1. microZedDA........................................................................................................................ 15

3.1.2. microZedAD ........................................................................................................................ 15

3.2

IGITAL

UTPUTS

.......................................................................................................................... 16

3.2.1. microZedCN1DigitalDirection ............................................................................................. 16

3.2.2. microZedCN1DO ................................................................................................................ 16

3.2.3. microZedCN1DI .................................................................................................................. 16

3.3

I/O

.............................................................................................................................................. 17

3.3.1. microZedAGHEncoder........................................................................................................ 17

3.3.2. microZedAGHGenerator..................................................................................................... 17

3.4

REAL

TIME EXPERIMENTS

IMPLEMENTATION

.................................................................................... 18

3.5

OOLS

.......................................................................................................................................... 21

3.5.1. RT-DAC Zynq Detect.......................................................................................................... 21

3.5.2. RT-DAC Zynq Status .......................................................................................................... 22

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INTRODUCTION AND GENERAL DESCRIPTION

1.1 G

ENERAL INFORMATION

The RT-DAC/Zynq is a multifunction analog and digital I/O board dedicated to real-

time data acquisition and control in the Windows , environments. The board contains

a XilinxFPGA chip. All boards are built as the OMNI version. It means the boards

can be reconfigured to introduce a new functionality of all inputs and outputs without

any hardware modification.

The default configuration of the FPGA chip accepts signals from incremental

encoders and generates PWM outputs, typical for mechatronic control applications

and is equipped with the general purpose digital input/outputs (GPIO), A/D and D/A

converters, timers, counters, frequency meters and chronometers.

The controller of the RT-DAC/Zynq system uses MicroZed development board as

calculation and front-end signal processing unit. The board includes Zynq SoC circuit

and consists of two ARM A9 processors and the FPGA fabric (see Fig.1.1). The

MicroZed is plugged-into a carrier board, which establishes interfaces to the

measurement and actuator signals.

Figure 1.1. The architecture of the heterogeneous RT-DAC/Zynq controller.

The ARM processors operate in Asymmetric Multiprocessing mode. The ARM1

processor runs Linux operating system. It runs all non-real-time tasks like file system

support, on-line monitoring and communication with a user. The second processor

runs real-time tasks generated automatically from the Simulink diagrams. AMP

configuration separates the execution of Linux critical sections from the real-time

task, which leads to small real-time jitter level.

Both processors communicate by a shared memory buffer. The communication

causes the Linux application to operate as supervisors to the real-time task, which in

turn responds for direct processing of RT-DAC/Zynq signals.

The FPGA is responsible for front-end signal processing. It generates PWMs for

the DC drives, processes encodes waves and establishes an interface to the general

purpose I/Os.

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1.1 S

PECIFICATION

Analog Inputs

Channels: 16 single-ended, multiplexed

Resolution: 14 bit

Input ranges: ±10V, programmable gain (x1, x2, x4, x8, x16)

Conversion

time:

5.4 µs

Trigger: all the A/D channels are scanned automatically

when data are required

Reference

voltage:

on-board

Analog Outputs

Channels: 4

Resolution: 14 bit

Output range: ±10V, ±5V

Settling time: 10 µs (to 0.01%)

Reference

voltage:

on-board

Digital Input/ Output

Channels: 26 bi-directional, direction setting; 8

channels shared with PWM outputs; 8

channels shared with 4 incremental encoder

channels

Direction: bi-directional, individually software

programmable

Input voltage: VIH = 2.0V÷3.6V, VIL = - 0.5V÷0.8V

Output voltage: VOH = 2.4V (min), VOL = 0.4V (max)

Output current: 2mA per channel

Standard: LVTTL

PWM Outputs

Channels: 8

Resolution: 32 bits for both High and Low states

Base frequency: 10ns resolution for both High and Low states

Incremental encoders

Channels: 4

Output: 32 bit counter

Index -

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1.2

SYSTEM COMPONENTS

To use the RT-DAC/Zynq system the following software and hardware

components are required:

Hardware

•RT-DAC/Zynq unit. SD card plugged into the RT-DAC/Zynq

•Power supply,

•Wiring and/or cables for the CN1 and CN2 connectors. Optionally wiring

terminal board.

•Ethernet cable, optional USB mini b cable

Software

•Toolbox for MATLAB/Simulink

•SD cart contents: Petalinux and configuration files



MATLAB cannot be installed in the “Program Files” directory (name

of the directory cannot include space).

Manuals:

•User’s Manual

1.3

SOFTWARE INSTALLATION

Insert the installation CD and follow the displayed commands.

Remember that it is time consuming procedure to be executed (approx. 5

minutes). Simultaneously with the installation of the RT-DAC/Zynq toolbox it is

installed the Linaro cross-compiler.

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1.4 P

ETALINUX

The ARM1 processor runs the PetaLinux version 2016.3 operating system. The

system boots from SD card and contains at least the following files:

•BOOT.BIN – contains the First Stage Boot Loader (FSBL), bitstream for the

FPGA fabric and U-Boot. The Zynq circuit automatically looks for this file at

the SD card, downloads bitstream to the FPGA, runs FSBL and finally runs

U-Boot.

•image.ub – compressed image of the Linux file system, processed by the

U-Boot. The file is uncompressed during booting phase and applied to

create the RAM disk Linux file system. Please remember that the file

system is of RAM disk type and any changes to the files will be lost

after turning off the power or reloading the system. The only option of

permanent changes in the file system is to change the content of the

image.ub file or save files on the SD card.

•RTDACStartup – optional script executed by Linux during boot.

The PetaLinux 2016.3 project applied to the controller of the RT-DAC/Zynq model

can be available on request.

1.4.1. RTDACS

TARTUP

The script RTDACStartup is located at the SD card and contains commands

executed by Linux during the boot phase. It contains the commands described in the

table below.

Commands Description

echo 953 > /sys/class/gpio/export

echo out > /sys/class/gpio/gpio953/direction

Optional. Configuration of the GPIO of the

LED on the MicroZed board. Required to

support heartbeat monitoring of the real-

time applications.

ifconfig eth0 192.168.1.102 Set IP address of the Ethernet cable port

./ExtModeTunnel.elf &

Run application responsible for the

communication in the external

communication mode

./uZServer.elf &

Run application responsible for the

communication with the real-time task and

with the FPGA registers

./elfio.elf uZSimulink.elf -v

./rwmem.elf 0x42800008 4883

./rwmem.elf 0x42800004 1

./rwmem.elf 0xFFFFFFF0 0x30000000

Optional. Commands to start the real-time

application immediately after the booting

of the Linux.

The RTDACStartup file can be modified by a user on request.

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1.4.2. FTP

The file system on the SD card is accessible by FTP protocol. The login is root.

The password is not required.

1.4.3. T

ELNET

A user can connect to the board by Telnet protocol. The login is root and the

password is root.

1.4.4. W

ERVER

An HTTP server is running by Petalinux. The address

http://192.168.1.102/cgi-bin/uZCGI

presents a table that contains diagnostic information.

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