Infineon Technologies Cypress CYW20733 Manuel utilisateur

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CYW20733

Single-Chip Bluetooth Transceiver

Wireless Input Devices

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document No. 002-14859 Rev. *S Revised November 9, 2017

The Cypress CYW20733 is a Bluetooth 3.0 + EDR compliant, stand-alone baseband processor with an integrated 2.4 GHz trans-

ceiver. The device is ideal for applications in wireless input devices including game controllers, keyboards, and joysticks. Built-in

firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications. The

CYW20733 radio has been designed to provide low power, low cost, and robust communications for applications operating in the

globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification 3.0 + EDR. The single-

chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires minimal exter-

nal components to make a fully compliant Bluetooth device. The CYW20733 is available in three package options: a 81-pin, 8 mm ×

8 mm FBGA, a 121-pin, 9 mm × 9 mm FBGA, and a 56-pin, 7 mm x 7 mm QFN.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Features

■Integrated LDO to reduce BOM cost

■Bluetooth specification 3.0 + EDR compatible

■Bluetooth HID profile version 1.1 compliant

■Bluetooth Device ID profile version 1.3 compliant

■Supports AFH

■Excellent receiver sensitivity

■On-chip support for common keyboard and mouse inter-

faces eliminates external processor

■Infrared (IR) modulator

■IR learning

■Integrated 200 mW filterless Class-D audio amplifier

■Triac control

■Triggered Broadcom Fast Connect

■One I/O capable of sinking 100 mA for high- current drive

applications

■Programmable key scan matrix interface, up to 8 × 20 key-

scanning matrix

■Three-axis quadrature signal decoder

■On-chip support for serial peripheral interface (master and

slave modes)

■Broadcom Serial Communications Interface (compatible

with Philips® I2C slaves)

■Two independent half-duplex PCM/I2S interfaces

■Real-time clock supported with 32.768 kHz oscillator

■Programmable output power control meets Class 2 or

Class 3 requirements

■On-chip PA with a maximum output power of +10dBm with-

out external component

■Integrated ARM7TDMI-S™-based microprocessor core

■On-chip power on reset (POR)

■On-chip software control power management unit

■Three package types available:

❐81-pin FBGA package (8 mm × 8 mm)

❐121-pin FBGA package (9 mm × 9 mm)

❐56-pin QFN package (7 mm x 7 mm)

■RoHS compliant

Applications

■Game controllers

■Wireless pointing devices: mice, trackballs

■Wireless keyboards

■Joysticks

■Point-of-sale (POS) input devices

■Remote controls

■Home automation

■3D glasses

Broadcom Part Number Cypress Part Number

BCM20733 CYW20733

BCM20733A3KFB1G CYW20733A3KFB1G

BCM20733A3KFB2G CYW20733A3KFB2G

BCM20733A3KML1G CYW20733A3KML1G

Document No. 002-14859 Rev. *S Page 2 of 67

CYW20733

Figure 1. Functional Block Diagram

Keyboard

Matrix

Scanner

w/FIFO

3-Axis

Mouse

Signal

Controller

Processing

Unit

(ARM7)

System Bus

Bluetooth

Baseband

Core

2.4 GHz

Radio

RF Control

and Data

T/R

Switch

RF I/O

GPIO

Control/

Status

Registers

Frequency

Synthesizer

57 GPIO Pins

Ref Xtal

LDO

CTRL

I/O Ring Bus

I/O Ring

Control

Registers

Peripheral

Interface

Block

1.2V VDDC

Domain

VDDO Domain

WAKE

1.2V

LDO

1.62V -3.6V

1.2V

VDDC

Volt. Trans

BSC/SPI

Master

Interface

(BSC is I2C-

compat)

SDA/

MOSI

SCK

6 quadrature inputs

(3 pair) + Hi -current

Driver Controls

8 x 20

Scan

Matrix

57 GPIO

32 kHz

LPCLK

28 ADC

Inputs

24 MHz

AutoCal

MISO

1.2V VDDRF

Domain

PWM

WDT

128 kHz

LPO

÷4

32 kHz

LPCLK

128 kHz

LPCLK

32 kHz Xtal (opƟonal)

Power

1.2V

POR

1.2V

Test

UART

I/O

Mod.

and

Learning

SPI

M/S

MIA

POR

CT ɇѐ

ADC

28 ADC

Inputs

VSS,

VDDO,

VDDC

Periph

UART

RTSN

CTSN

Muxed on GPIO

384K

ROM

80K

RAM

High

Sink IO

PMU

Digital

Audio

Block

RTSN

CTSN

Class-D

Driver

Speaker

Out

Document No. 002-14859 Rev. *S Page 3 of 67

CYW20733

Contents

1.Functional Description ....................................... 4

1.1 Integrated Radio Transceiver .............................. 4

1.1.1 Transmitter Path ...................................... 4

1.1.2 Receiver Path .......................................... 4

1.1.3 Local Oscillator ........................................ 4

1.1.4 Calibration ............................................... 4

1.1.5 Internal LDO Regulator ............................ 4

1.2 Microprocessor Unit ............................................ 5

1.2.1 EEPROM Interface .................................. 5

1.2.2 Serial Flash Interface ............................... 5

1.2.3 Internal Reset .......................................... 5

1.2.4 External Reset ......................................... 6

1.3 Bluetooth Baseband Core ................................... 6

1.3.1 Frequency Hopping Generator ................ 6

1.3.2 E0 Encryption .......................................... 6

1.3.3 Link Control Layer ................................... 6

1.3.4 Adaptive Frequency Hopping .................. 6

1.3.5 Bluetooth Version 3.0 Features ............... 6

1.3.6 Test Mode Support .................................. 7

1.4 Peripheral Transport Unit (PTU) ......................... 7

1.4.1 Broadcom Serial Control Interface .......... 7

1.4.2 UART Interface ........................................ 8

1.5 PCM Interface ..................................................... 9

1.5.1 System Diagram ...................................... 9

1.5.2 Slot Mapping .......................................... 10

1.5.3 Frame Synchronization .......................... 10

1.5.4 Data Formatting ..................................... 10

1.6 I2S Interface ...................................................... 10

1.7 Clock Frequencies ............................................ 10

1.7.1 Crystal Oscillator ................................... 10

1.8 GPIO Port .......................................................... 12

1.9 Keyboard Scanner ............................................ 12

1.9.1 Theory of Operation ............................... 13

1.10 Mouse Quadrature Signal Decoder ................... 13

1.10.1 Theory of Operation ............................... 13

1.11 ADC Port ........................................................... 13

1.12 PWM ................................................................. 14

1.13 Serial Peripheral Interface ................................. 15

1.14 Infrared Modulator ..............................................18

1.15 Infrared Learning ................................................19

1.16 Shutter Control for 3D Glasses ..........................19

1.17 Triac Control .......................................................20

1.18 Cypress Proprietary Control Signalling

and Triggered Broadcom Fast Connect .............20

1.19 Integrated Filterless Class-D Audio Amplifier .....20

1.20 High-Current I/O .................................................21

1.21 Power Management Unit ....................................22

1.21.1 RF Power Management ..........................22

1.21.2 Host Controller Power Management ......22

1.21.3 BBC Power Management .......................22

2.Pin Assignments............................................... 23

2.1 Ball Maps ...........................................................29

2.1.1 81-Pin FBGA Ball Map ...........................29

2.1.2 121-Pin FBGA Ball Map .........................31

2.1.3 56-Pin QFN Diagram ..............................32

3.Specifications.................................................... 33

3.1 Electrical Characteristics ....................................33

3.2 RF Specifications ...............................................37

3.3 Timing and AC Characteristics ...........................39

3.3.1 UART Timing ..........................................39

3.3.2 SPI Timing ..............................................40

3.3.3 BSC Interface Timing .............................41

3.3.4 PCM Interface Timing .............................43

3.3.5 I2S Timing ...............................................48

4.Mechanical Information.................................... 53

4.0.1 Tape Reel and Packaging

Specifications .........................................56

5.Ordering Information ........................................ 62

6.IoT Resources ................................................... 62

A.Acronyms and Abbreviations.......................... 62

Document History........................................................... 64

Sales, Solutions, and Legal Information ...................... 67

Document No. 002-14859 Rev. *S Page 4 of 67

CYW20733

1. Functional Description

1.1 Integrated Radio Transceiver

The CYW20733 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has

been designed to provide low power, low cost, robust communications for applications operating in the globally available 2.4 GHz

unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 + EDR and meets or exceeds the requirements to

provide the highest communication link quality of service.

1.1.1 Transmitter Path

The CYW20733 features a fully integrated zero IF transmitter. The baseband transmit data is GFSK modulated in the modem block

and upconverted to the 2.4 GHz ISM band. The transmit path consists of signal filtering,

I/Q upconversion, output power amplification, and RF filtering. It also incorporates the /4-DQPSK and 8-DPSK modulation schemes,

which support the 2 Mbps and 3 Mbps enhanced data rates, respectively.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and

8-DPSK signals. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the

transmitted signal and is much more stable than direct VCO modulation schemes.

Power Amplifier

The integrated power amplifier (PA) for the CYW20733 can transmit at a maximum power of +4 dBm for class 2 operation. The transmit

power levels are for basic rate and EDR. Due to the linear nature of the PA, combined with some integrated filtering, no external filters

are required for meeting Bluetooth and regulatory harmonic and spurious requirements.

The CYW20733 internal PA can deliver a maximum output power of +10 dBm for basic rate and +8 dBm for EDR with a flexible supply

range of 2.5V to 3.0V.

1.1.2 Receiver Path

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation

enables the CYW20733 to be used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYW20733 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

1.1.3 Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO

subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20733 uses an internal RF and IF

loop filter.

1.1.4 Calibration

The CYW20733 radio transceiver features an automated calibration scheme that is self-contained in the radio. No user interaction is

required during normal operation or during manufacturing to provide the optimal performance. Calibration will optimize the gain and

phase performance of all the major blocks within the radio to within 2% of optimal conditions. Calibrated blocks include filters, the

matching networks between key components, and key gain blocks. The calibration process corrects for both process and temperature

variations. It occurs transparently during normal operation and the setting time of the hops and will calibrate for temperature variations

as the device cools and heats during normal operation in its environment.

1.1.5 Internal LDO Regulator

To reduce the external BOM, the CYW20733 has an integrated 1.2V LDO regulator to provide power to the digital and RF circuits and

system components. The 1.2V LDO regulator operates from a 1.62V to 3.63V input supply with a 60 mA maximum load current.

In noisy environments, a ferrite bead may be needed between the digital and RF supply pins to isolate noise coupling and suppress

noise into the RF circuits.

Note: Always place the decoupling capacitors near the pins as close together as possible.

Document No. 002-14859 Rev. *S Page 5 of 67

CYW20733

1.2 Microprocessor Unit

The CYW20733 microprocessor unit (µPU) runs software from the link control (LC) layer up to the Human Interface Device (HID). The

microprocessor is based on an ARM7™ 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU

has 320 KB of ROM for program storage and boot-up, 80 KB of RAM for scratch-pad data, and patch RAM code.

The internal boot ROM allows for flexibility during power-on reset to enable the same device to be used in various configurations,

including UART, and with an external serial EEPROM or with an external flash memory. At power-up, the lower layer protocol stack

is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can

also support the integration of user applications.

1.2.1 EEPROM Interface

The CYW20733 provides the BSC (Broadcom Serial Control) master interface; the BSC is programmed by the CPU to generate four

different types of BSC transfers on the bus: read-only, write-only, combined read/write, and combined write/read. BSC supports both

low-speed and fast mode devices. The BSC is compatible with a Philips® I2C slave device, except that master arbitration (multiple

I2C masters contending for the bus) is not supported. Native support for Microchip® 24LC128, Microchip 24AA128, and STMicroelec-

tronics® M24128-BR is included.

The EEPROM can contain customer application configuration information, including: application code, configuration data, patches,

pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.

1.2.2 Serial Flash Interface

The CYW20733 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

Devices natively supported include the following:

■Atmel® AT25BCM512B

■MXIC MX25V512ZUI-20G

1.2.3 Internal Reset

The CYW20733 has an integrated power-on reset circuit that resets all circuits to a known power-on state.

Figure 1. Internal Reset Timing

VDDO

VDDOPOR

VDDC

VDDOPORthreshold

VDDOPORdelay

~2ms

VDDCPOR

VDDCPORthreshold

VDDCPORdelay

~2ms

BasebandReset

Crystal

warm‐up

delay:

~5ms

CrystalEnable

StartreadingEEPROMandfirmwareboot.

Document No. 002-14859 Rev. *S Page 6 of 67

CYW20733

1.2.4 External Reset

An external active-low reset signal, RESET_N, can be used to put the CYW20733 in the reset state. The RESET_N pin has an internal

pull-up resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after

the VDDO supply voltage level has been stabilized.

Figure 2. External Reset Timing

1.3 Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.

The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,

handles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data

into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these

functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/

RX data before sending over the air:

■Receive Functions: Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data de-whitening.

■Transmit Functions: Data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and

data whitening.

1.3.1 Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,

Bluetooth clock, and the device address.

1.3.2 E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide

minimal intervention.

1.3.3 Link Control Layer

The Link Control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit

(LCU). This layer consists of the command controller, which takes commands from the software, and other controllers that are

activated or configured by the command controller to perform the link control tasks. Each task performs in a different state in the

Bluetooth link controller. STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page

scan, inquiry, inquiry scan, and sniff.

1.3.4 Adaptive Frequency Hopping

The CYW20733 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map

selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop

map.

1.3.5 Bluetooth Version 3.0 Features

The CYW20733 is fully compliant with the Bluetooth 3.0 standard, including the following options:

RESET_N

Pulsewidth

>20µs

CrystalEnable

BasebandReset

StartreadingEEPROMandfirmwareboot.

Crystal

warm‐up

delay:

~5ms

Document No. 002-14859 Rev. *S Page 7 of 67

CYW20733

■Enhanced power control

■HCI read, encryption key size command

The CYW20733 supports all of the new Bluetooth version 2.1 features:

■Extended inquiry response

■Sniff subrating

■Encryption pause and resume

■Secure simple pairing

■Link supervision timeout changed event

■Erroneous data reporting

■Non-automatically flushable packet boundary flag

■Security Mode 4

1.3.6 Test Mode Support

The CYW20733 fully supports Bluetooth Test Mode, as described in Part 1 of the Bluetooth System Version 2.1 specification. This

includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

In addition to the standard Bluetooth test mode, the device supports enhanced testing features to simplify RF debugging and qualifi-

cation and type approval testing. These features include:

■Fixed frequency carrier wave (unmodulated) transmission

■Simplified type approval measurements (Japan)

■Aid in transmitter performance analysis

■Fixed frequency constant receiver mode

■Receiver output directed to I/O pin

■Direct BER measurements using standard RF test equipment

■Facilitated spurious emissions testing for receive mode

■Fixed frequency constant transmission

■8-bit fixed pattern or PRBS-9

■Modulated signal measurements with standard RF test equipment

■Connectionless transmitter test

■Hopping or fixed frequency

■Multiple packet types

■Multiple data patterns

■Connectionless receiver test

1.4 Peripheral Transport Unit (PTU)

1.4.1 Broadcom Serial Control Interface

The CYW20733 provides a 2-pin master BSC interface that can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. The BSC interface is compatible with I2C slave devices. The BSC does not support multimaster capability or flexible wait-

state insertion by either master or slave devices.

Listed below are the transfer clock rates supported by the BSC:

■100 kHz

■400 kHz

■800 kHz (Not a standard I2C-compatible speed.)

Document No. 002-14859 Rev. *S Page 8 of 67

CYW20733

■4 MHz maximum (Compatibility with high-speed I2C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

■Read (up to 127 bytes can be read)

■Write (up to 127 bytes can be written)

■Read-then-Write (Up to 127 bytes can be read, and up to 127 bytes can be written.)

■Write-then-Read (Up to 127 bytes can be written, and up to 127 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20733 are required on

both SCL and SDA for proper operation.

1.4.2 UART Interface

The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 1.5

Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI

command. The CYW20733 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The

interface supports the Bluetooth 3.0 UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

The UART clock is 24 MHz. The baud rate of the CYW20733 UART is controlled by two values. The first is a UART clock divisor (also

called the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (also called

the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to

eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end

of each bit time.

When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as 256 minus the chosen divisor. For

example, a divisor of 13 is stored as 256 – 13 = 243 = 0xF3.

The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert in the first

half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time. If either of these

two values is over eight, it is rounded to eight.

To compute the baud rate, the calculation is expressed as:

24 MHz ÷ ((16 × UART clock divisor) + total inserted 24-MHz clock cycles)

Table 2 contains example values to generate common baud rates.

Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during

normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud

rate registers.

The CYW20733 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.

Peripheral UART Interface

The CYW20733 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through

the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 3.

Table 2. Common Baud Rate Examples

Desired Baud Rate

(bps)

UART Clock Divi-

sor

Baud Rate Adjustment Actual Baud Rate

(bps)

Error

(%)

High Nibble Low Nibble

1500000 0xFF 0x00 0x00 1500000 0.00

921600 0xFF 0x05 0x05 923077 0.16

460800 0xFD 0x02 0x02 461538 0.16

230400 0xFA 0x04 0x04 230769 0.16

115200 0xF3 0x00 0x00 115385 0.16

57600 0xE6 0x00 0x00 57692 0.16

38400 0xD9 0x01 0x00 38400 0.00

28800 0xCC 0x00 0x00 28846 0.16

19200 0xB2 0x01 0x01 19200 0.00

14400 0x98 0x00 0x00 14423 0.16

9600 0x64 0x02 0x02 9600 0.00

Document No. 002-14859 Rev. *S Page 9 of 67

CYW20733

1.5 PCM Interface

The CYW20733 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device

generates the PCM_BCLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM

interface as inputs to the device.

The channels can be configured to either transmit or receive, but they must be assigned to different time slots. The two half-duplex

channels cannot be combined to form a single full-duplex channel.

1.5.1 System Diagram

Figure 3 shows options for connecting the device to a PCM codec device as a master or a slave.

Figure 3. PCM Interface with Linear PCM Codec

Table 3. CYW20733 Peripheral UART

Pin Name pUART_TX pUART_RX pUART_CTS_N pUART_RTS_N

Configured pin name P0 P2 P3 P1

P5 P4 P7 P6

P24 P25 P35 P30

P31 P33 – –

P32 P34 – –

PCMInterfaceSlaveMode

PCMCodec

(Master)

CYW20733

(Slave)

PCM_IN

PCM_BCLK

PCM_SYNC

PCM_OUT

PCMInterfaceMasterMode

PCMCodec

(Slave)

CYW20733

(Master)

PCM_IN

PCM_BCLK

PCM_SYNC

PCM_OUT

PCMInterfaceHybridMode

PCMCodec

(Hybrid)

CYW20733

(Hybrid)

PCM_IN

PCM_BCLK

PCM_SYNC

PCM_OUT

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