Exar XRT86VL30 Manuel utilisateur

Exar

Corporation 48720 Kato Road, Fremont CA, 94538

•

(510) 668-7000

•

FAX (510) 668-7017

•

www.exar.com

XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

2008 REV. 1.0.0

GENERAL DESCRIPTION

The XRT86VL30 is a single channel 1.544 Mbit/s or

2.048 Mbit/s DS1/E1/J1 framer and LIU integrated

solution featuring R

technology (Relayless,

Reconfigurable, Redundancy). The physical

interface is optimized with internal impedance, and

with the patented pad structure, the XRT86VL30

provides protection from power failures and hot

swapping.

The XRT86VL30 contains an integrated DS1/E1/J1

framer and LIU which provides DS1/E1/J1 framing

and error accumulation in accordance with ANSI/

ITU_T specifications. The framer has its own framing

synchronizer and transmit-receive slip buffers. The

slip buffers can be independently enabled or disabled

as required and can be configured to frame to the

common DS1/E1/J1 signal formats.

The Framer block contains its own Transmit and

Receive T1/E1/J1 Framing function. There are 3

Transmit HDLC controllers which encapsulate

contents of the Transmit HDLC buffers into LAPD

Message frames. There are 3 Receive HDLC

controllers which extract the payload content of

Receive LAPD Message frames from the incoming

T1/E1/J1 data stream and write the contents into the

Receive HDLC buffers. The framer also contains a

Transmit and Overhead Data Input port, which

permits Data Link Terminal Equipment direct access

to the outbound T1/E1/J1 frames. Likewise, a

Receive Overhead output data port permits Data Link

Terminal Equipment direct access to the Data Link

bits of the inbound T1/E1/J1 frames.

The XRT86VL30 fully meets all of the latest T1/E1/J1

specifications: ANSI T1/E1.107-1988, ANSI T1/

E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/

E1.408-1990, AT&T TR 62411 (12-90) TR54016, and

ITU G-703, G.704, G706 and G.733, AT&T Pub.

43801, and ETS 300 011, 300 233, JT G.703, JT

G.704, JT G706, I.431. Extensive test and diagnostic

functions include Loop-backs, Boundary scan,

Pseudo Random bit sequence (PRBS) test pattern

generation, Performance Monitor, Bit Error Rate

(BER) meter, forced error insertion, and LAPD

unchannelized data payload processing according to

ITU-T standard Q.921.

APPLICATIONS AND FEATURES (NEXT PAGE)

IGURE

1. XRT86VL30 S

INGLE

HANNEL

DS1 (T1/E1/J1) F

RAMER

/LIU C

OMBO

Performance

Monitor

PRBS

Generator &

Analyser

HDLC/LAPD

Controllers

LIU &

Loopback

Control

DMA

Interface

Signaling &

Alarms JTAG

ALE_AS

RDY_DTACK

µP

Select

A[11:0]D[7:0]

Microprocessor

Interface

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1.544-16.384 Mbit/s

Local PCM

Highway

ST-BUS

2-Frame

Slip Buffer

Elastic Store

Tx Serial

Data In Tx LIU

Interface

2-Frame

Slip Buffer

Elastic Store

Rx LIU

Interface

Rx Framer

Rx Serial

Data Out

RTIP

RRING

TTIP

TRING

External Data

Link Controller

Tx Overhead In Rx Overhead Out

XRT86VL30

Tx Framer

LLB LB

System (Terminal) Side

Line Side

1:1 Turns Ratio

1:2 Turns Ratio

Memory

Intel/Motorola µP

Configuration, Control &

Status Monitor

RxLOS

TxON

INT

XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. 1.0.0

APPLICATIONS

•

High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems

•

SONET/SDH terminal or Add/Drop multiplexers (ADMs)

•

T1/E1/J1 add/drop multiplexers (MUX)

•

Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1

•

Digital Access Cross-connect System (DACs)

•

Digital Cross-connect Systems (DCS)

•

Frame Relay Switches and Access Devices (FRADS)

•

ISDN Primary Rate Interfaces (PRA)

•

PBXs and PCM channel bank

•

T3 channelized access concentrators and M13 MUX

•

Wireless base stations

•

ATM equipment with integrated DS1 interfaces

•

Multichannel DS1 Test Equipment

•

T1/E1/J1 Performance Monitoring

•

Voice over packet gateways

•

Routers

FEATURES

•

Supports SSM Synchronization Messaging per ANSI T1.101-1999 and ITU G.704

•

Supports a Customized Section 13 - Synchronization Interface in G.703 at 1.544MHz

•

Independent, full duplex DS1 Tx and Rx Framer/LIUs

•

Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz

asynchronous back plane connections with jitter and wander attenuation

•

Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel

multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus

•

Programmable output clocks for Fractional T1/E1/J1

•

Supports Channel Associated Signaling (CAS)

•

Supports Common Channel Signalling (CCS)

•

Supports ISDN Primary Rate Interface (ISDN PRI) signaling

•

Extracts and inserts robbed bit signaling (RBS)

•

3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 /

buffer 1)

•

HDLC Controllers Support SS7

•

Timeslot assignable HDLC

•

V5.1 or V5.2 Interface

•

Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface

every 1 second or for a single transmission

•

Alarm Indication Signal with Customer Installation signature (AIS-CI)

XRT86VL30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

•

Remote Alarm Indication with Customer Installation (RAI-CI)

•

Gapped Clock interface mode for Transmit and Receive.

•

Intel/Motorola and Power PC interfaces for configuration, control and status monitoring

•

Parallel search algorithm for fast frame synchronization

•

Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)

•

Direct access to D and E channels for fast transmission of data link information

•

PRBS, QRSS, and Network Loop Code generation and detection

•

Programmable Interrupt output pin

•

Supports programmed I/O and DMA modes of Read-Write access

•

The framer block encodes and decodes the T1/E1/J1 Frame serial data

•

Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms

•

Detects OOF, LOF, LOS errors and COFA conditions

•

Loopbacks: Local (LLB) and Line remote (LB)

•

Facilitates Inverse Multiplexing for ATM

•

Performance monitor with one second polling

•

Boundary scan (IEEE 1149.1) JTAG test port

•

Accepts external 8kHz Sync reference

•

1.8V Inner Core

•

3.3V CMOS operation with 5V tolerant inputs

•

128-pin LQFP and 80-pin LQFP package with

-40

C to +85

operation

ORDERING INFORMATION

ART

UMBER

ACKAGE

PERATING

EMPERATURE

ANGE

XRT86VL30IV 128 Pin LQFP(14x20x1.4mm) -40

C to +85

XRT86VL30IV80 80 Pin LQFP (12x12x1.4mm) -40

C to +85

XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. 1.0.0

LIST OF PARAGRAPHS

1.0 REGISTER DESCRIPTIONS - T1 MODE .................................................................................................9

2.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS .......................................................................124

XRT86VL30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

LIST OF FIGURES

Figure 1.: XRT86VL30 2-channel DS1 (T1/E1/J1) Framer/LIU Combo .............................................................................1

XRT86VL30

III

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. 1.0.0

LIST OF TABLES

Table 1:: Register Summary ..............................................................................................................................................4

Table 2:: Clock Select Register(CSR) Hex Address: 0x0100 ..........9

Table 3:: Line Interface Control Register (LICR) Hex Address: 0x0101 ...............11

Table 4:: Framing Select Register (FSR) Hex Address: 0x0107 ....................13

Table 5:: Alarm Generation Register (AGR) Hex Address: 0x0108 ......................15

Table 6:: yellow alarm duration and format when one second rule is not enforced .........................................................16

Table 7:: yellow alarm format when one second rule is enforced ....................................................................................17

Table 8:: Synchronization MUX Register (SMR) Hex Address: 0x0109 ...................19

Table 9:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0x010A ....................22

Table 10:: Framing Control Register (FCR) Hex Address: 0x010B ..................24

Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0x010C ....................25

Table 12:: Receive Signaling Change Register 0 (RSCR 0) Hex Address: 0x010D ...........27

Table 13:: Receive Signaling Change Register 1(RSCR 1) Hex Address: 0x010E .......27

Table 14:: Receive Signaling Change Register 2 (RSCR 2) Hex Address: 0x010F .........27

Table 15:: Receive In Frame Register (RIFR) Hex Address: 0x0112 ...................28

Table 16:: Data Link Control Register (DLCR1) Hex Address: 0x0113 ....................28

Table 17:: Transmit Data Link Byte Count Register (TDLBCR1) Hex Address: 0x0114 ....................31

Table 18:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0x0115 ...................32

Table 19:: Slip Buffer Control Register (SBCR) Hex Address: 0x0116 ......................33

Table 20:: FIFO Latency Register (FFOLR) Hex Address: 0x0117 ................34

Table 21:: DMA 0 (Write) Configuration Register (D0WCR) Hex Address: 0x0118 ..................35

Table 22:: DMA 1 (Read) Configuration Register (D1RCR) Hex Address: 0x0119 ..................36

Table 23:: Interrupt Control Register (ICR) Hex Address: 0x011A ......................37

Table 24:: LAPD Select Register (LAPDSR) Hex Address: 0x011B .................37

Table 25:: Customer Installation Alarm Generation Register (CIAGR) Hex Address: 0x011C ........................38

Table 26:: Performance Report Control Register (PRCR) Hex Address: 0x011D .....................39

Table 27:: Gapped Clock Control Register (GCCR) Hex Address: 0x011E ..................40

Table 28:: Transmit Interface Control Register (TICR) Hex Address:0x0120 .....................41

Table 29:: Transmit Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ...........................................43

Table 30:: Transmit Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) ............................................44

Table 31:: PRBS Control & Status Register (PRBSCSR0) Hex Address: 0x0121 ...............45

Table 32:: Receive Interface Control Register (RICR) Hex Address: 0x0122 ..............47

Table 33:: Receive Interface Speed When Multiplexed Mode is Disabled (TxMUXEN = 0) ............................................49

Table 34:: Receive Interface Speed when Multiplexed Mode is Enabled (TxMUXEN = 1) .............................................50

Table 35:: PRBS Control & Status Register (PRBSCSR1) Hex Address: 0x0123 .....................51

Table 36:: Loopback Code Control Register (LCCR) Hex Address: 0x0124 ................53

Table 37:: Transmit Loopback Coder Register (TLCR) Hex Address: 0x0125 ..............55

Table 38:: Receive Loopback Activation Code Register (RLACR) Hex Address: 0x0126 .................55

Table 39:: Receive Loopback Deactivation Code Register (RLDCR) Hex Address: 0x0127 ...................55

Table 40:: Defect Detection Enable Register (DDER) Hex Address: 0x0129 ...............56

Table 41:: Transmit SPRM Control Register (TSPRMCR) Hex Address: 0x0142 .................56

Table 42:: Data Link Control Register (DLCR2) Hex Address: 0x0143 ...................57

Table 43:: Transmit Data Link Byte Count Register (TDLBCR2) Hex Address: 0x0144 ...................59

Table 44:: Receive Data Link Byte Count Register (RDLBCR2) Hex Address: 0x0145 ..................60

Table 45:: Data Link Control Register (DLCR3) Hex Address: 0x0153 ..................61

Table 46:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0x0154 ...................63

Table 47:: Receive Data Link Byte Count Register (RDLBCR3) Hex Address: 0x0155 ..................64

Table 48:: Device ID Register (DEVID) Hex Address: 0x01FE ............65

Table 49:: Revision ID Register (REVID) Hex Address: 0x01FF ...........65

Table 50:: Transmit Channel Control Register 0-23 (TCCR 0-23) Hex Address: 0x0300 to 0x0317 .....................66

Table 51:: Transmit User Code Register 0-23 (TUCR 0-23) Hex Address: 0x0320 to 0x0337 ................68

Table 52:: Transmit Signaling Control Register 0-23 (TSCR 0-23) Hex Address: 0x0340 to 0x0357 .......................69

Table 53:: Receive Channel Control Register 0-23 (RCCR 0-23) Hex Address: 0x0360 to 0x0377 ...................71

Table 54:: Receive User Code Register 0-23 (RUCR 0-23) Hex Address: 0x0380 to 0x0397 ..............73

Table 55:: Receive Signaling Control Register 0-23 (RSCR 0-23) Hex Address: 0x03A0 to 0x03B7 ....................74

Table 56:: Receive Substitution Signaling Register 0-23 (RSSR 0-23) Hex Address: 0x03C0 to 0x03D7 ...................76

Table 57:: Receive Signaling Array Register 0 to 23 (RSAR 0-23) Hex Address: 0x0500 to 0x0517 ...................77

Table 58:: LAPD Buffer 0 Control Register (LAPDBCR0) Hex Address: 0x0600 ....................................78

XRT86VL30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

Table 59:: LAPD Buffer 1 Control Register (LAPDBCR1) Hex Address: 0x0700 ......................................78

Table 60:: PMON Receive Line Code Violation Counter MSB (RLCVCU) Hex Address: 0x0900 .................79

Table 61:: PMON Receive Line Code Violation Counter LSB (RLCVCL) Hex Address: 0x0901 ................79

Table 62:: PMON Receive Framing Alignment Bit Error Counter MSB (RFAECU) Hex Address: 0x0902 ...................80

Table 63:: PMON Receive Framing Alignment Bit Error Counter LSB (RFAECL) Hex Address: 0x0903 ....................80

Table 64:: PMON Receive Severely Errored Frame Counter (RSEFC) Hex Address: 0x0904 ...................81

Table 65:: PMON Receive CRC-6 BIT Error Counter - MSB (RSBBECU) Hex Address: 0x0905 .................82

Table 66:: PMON Receive CRC-6 Bit Error Counter - LSB (RSBBECL) Hex Address: 0x0906 ................82

Table 67:: PMON Receive Slip Counter (RSC) Hex Address: 0x0909 ............... 83

Table 68:: PMON Receive Loss of Frame Counter (RLFC) Hex Address: 0x090A ................83

Table 69:: PMON Receive Change of Frame Alignment Counter (RCFAC) Hex Address: 0x090B ................83

Table 70:: PMON LAPD1 Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0x090C .................84

Table 71:: PRBS Bit Error Counter MSB (PBECU) Hex Address: 0x090D .................84

Table 72:: PRBS Bit Error Counter LSB (PBECL) Hex Address: 0x090E .................84

Table 73:: Transmit Slip Counter (TSC) Hex Address: 0x090F ...............85

Table 74:: Excessive Zero Violation Counter MSB (EZVCU) Hex Address: 0x0910 .................85

Table 75:: Excessive Zero Violation Counter LSB (EZVCL) Hex Address: 0x0911 ................. 85

Table 76:: PMON LAPD2 Frame Check Sequence Error Counter 2 (LFCSEC2) Hex Address: 0x091C .................86

Table 77:: PMON LAPD2 Frame Check Sequence Error Counter 3 (LFCSEC3) Hex Address: 0x092C .................86

Table 78:: Block Interrupt Status Register (BISR) Hex Address: 0x0B00 .................... 87

Table 79:: Block Interrupt Enable Register (BIER) Hex Address: 0x0B01 ...................89

Table 80:: Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0x0B02 .....................91

Table 81:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0x0B03 ......................93

Table 82:: Framer Interrupt Status Register (FISR) Hex Address: 0x0B04 ...................94

Table 83:: Framer Interrupt Enable Register (FIER) Hex Address: 0x0B05 ...................96

Table 84:: Data Link Status Register 1 (DLSR1) Hex Address: 0x0B06 ................98

Table 85:: Data Link Interrupt Enable Register 1 (DLIER1) Hex Address: 0x0B07 .................100

Table 86:: Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0x0B08 ...................102

Table 87:: Slip Buffer Interrupt Enable Register (SBIER) Hex Address: 0x0B09 ..................105

Table 88:: Receive Loopback Code Interrupt and Status Register (RLCISR) Hex Address: 0x0B0A ...................107

Table 89:: Receive Loopback Code Interrupt Enable Register (RLCIER) Hex Address: 0x0B0B ...................108

Table 90:: Excessive Zero Status Register (EXZSR) Hex Address: 0x0B0E ................ 109

Table 91:: Excessive Zero Enable Register (EXZER) Hex Address: 0x0B0F ..............109

Table 92:: SS7 Status Register for LAPD1 (SS7SR1) Hex Address: 0x0B10 ................110

Table 93:: SS7 Enable Register for LAPD1 (SS7ER1) Hex Address: 0x0B11 ..............110

Table 94:: RxLOS/CRC Interrupt Status Register (RLCISR) Hex Address: 0x0B12 ...............111

Table 95:: RxLOS/CRC Interrupt Enable Register (RLCIER) Hex Address: 0x0B13 ...............111

Table 96:: Data Link Status Register 2 (DLSR2) Hex Address: 0x0B16 ...............112

Table 97:: Data Link Interrupt Enable Register 2 (DLIER2) Hex Address: 0x0B17 .................114

Table 98:: SS7 Status Register for LAPD2 (SS7SR2) Hex Address: 0x0B18 ................116

Table 99:: SS7 Enable Register for LAPD2 (SS7ER2) Hex Address: 0x0B19 ................116

Table 100:: Data Link Status Register 3 (DLSR3) Hex Address: 0x0B26 .............117

Table 101:: Data Link Interrupt Enable Register 3 (DLIER3) Hex Address: 0x0B27 ..............119

Table 102:: SS7 Status Register for LAPD3 (SS7SR3) Hex Address: 0x0B28 .............121

Table 103:: SS7 Enable Register for LAPD3 (SS7ER3) Hex Address: 0x0B29 ............121

Table 104:: Customer Installation Alarm Status Register (CIASR) Hex Address: 0x0B40 ..................122

Table 105:: Customer Installation Alarm Status Register (CIAIER) Hex Address: 0x0B41 ..................123

Table 106:: LIU Channel Control Register 0 (LIUCCR0) Hex Address: 0x0F00 ............124

Table 107:: Equalizer Control and Transmit Line Build Out ...........................................................................................126

Table 108:: LIU Channel Control Register 1 (LIUCCR1) Hex Address: 0x0F01 ........... 127

Table 109:: LIU Channel Control Register 2 (LIUCCR2) Hex Address: 0x0F02 ............129

Table 110:: LIU Channel Control Register 3 (LIUCCR3) Hex Address: 0x0F03 ........... 131

Table 111:: LIU Channel Control Interrupt Enable Register (LIUCCIER) Hex Address: 0x0F04 .................133

Table 112:: LIU Channel Control Status Register (LIUCCSR) Hex Address: 0x0F05 ................ 135

Table 113:: LIU Channel Control Interrupt Status Register (LIUCCISR) Hex Address: 0x0F06 .................... 138

Table 114:: LIU Channel Control Cable Loss Register (LIUCCCCR) Hex Address: 0x0F07 ...............139

Table 115:: LIU Channel Control Arbitrary Register 1 (LIUCCAR1) Hex Address: 0x0F08 ..................140

Table 116:: LIU Channel Control Arbitrary Register 2 (LIUCCAR2) Hex Address: 0x0F09 ..................... 140

Table 117:: LIU Channel Control Arbitrary Register 3 (LIUCCAR3) Hex Address: 0x0F0A .....................140

Table 120:: LIU Channel Control Arbitrary Register 6 (LIUCCAR6) Hex Address: 0x0F0D .....................141

XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. 1.0.0

Table 118:: LIU Channel Control Arbitrary Register 4 (LIUCCAR4) Hex Address: 0x0F0B .....................141

Table 119:: LIU Channel Control Arbitrary Register 5 (LIUCCAR5) Hex Address: 0x0F0C .....................141

Table 121:: LIU Channel Control Arbitrary Register 7 (LIUCCAR7) Hex Address: 0x0F0E .....................142

Table 122:: LIU Channel Control Arbitrary Register 8 (LIUCCAR8) Hex Address: 0x0F0F .....................142

Table 123:: LIU Global Control Register 0 (LIUGCR0) Hex Address: 0x0FE0 .............143

Table 124:: LIU Global Control Register 1 (LIUGCR1) Hex Address: 0x0FE1 .............144

Table 125:: LIU Global Control Register 2 (LIUGCR2) Hex Address: 0x0FE2 .............145

Table 126:: LIU Global Control Register 3 (LIUGCR3) Hex Address: 0x0FE4 .............146

Table 127:: LIU Global Control Register 4 (LIUGCR4) Hex Address: 0x0FE9 .............147

Table 128:: LIU Global Control Register 5 (LIUGCR5) Hex Address: 0x0FEA .............148

XRT86VL30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

DESCRIPTION OF THE CONTROL REGISTERS - T1 MODE

All address on this register description is shown in HEX format.

ABLE

1: R

EGISTER

UMMARY

UNCTION

YMBOL

Control Registers (0x0100 - 0x01FF)

Clock and Select Register CSR 0x0100

Line Interface Control Register LICR 0x0101

Reserved - 0x0102 - 0x0106

Framing Select Register FSR 0x0107

Alarm Generation Register AGR 0x0108

Synchronization MUX Register SMR 0x0109

Transmit Signaling and Data Link Select Register TSDLSR 0x010A

Framing Control Register FCR 0x010B

Receive Signaling & Data Link Select Register RSDLSR 0x010C

Receive Signaling Change Register 0 RSCR0 0x010D

Receive Signaling Change Register 1 RSCR1 0x010E

Receive Signaling Change Register 2 RSCR2 0x010F

Reserved - E1 mode only - 0x0110 -

0x0111

Receive In-Frame Register RIFR 0x0112

Data Link Control Register 1 DLCR1 0x0113

Transmit Data Link Byte Count Register 1 TDLBCR1 0x0114

Receive Data Link Byte Count Register 1 RDLBCR1 0x0115

Slip Buffer Control Register SBCR 0x0116

FIFO Latency Register FIFOLR 0x0117

DMA 0 (Write) Configuration Register D0WCR 0x0118

DMA 1 (Read) Configuration Register D1RCR 0x0119

Interrupt Control Register ICR 0x011A

LAPD Select Register LAPDSR 0x011B

Customer Installation Alarm Generation Register CIAGR 0x011C

Performance Report Control Register PRCR 0x011D

Gapped Clock Control Register GCCR 0x011E

Transmit Interface Control Register TICR 0x0120

BERT Control & Status - Register 0 BERTCSR0 0x0121

Receive Interface Control Register RICR 0x0122

XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. 1.0.0

BERT Control & Status - Register 1 BERTCSR1 0x0123

Loopback Code Control Register - Code 0 LCCR0 0x0124

Transmit Loopback Code Register TLCR 0x0125

Receive Loopback Activation Code Register - Code 0 RLACR0 0x0126

Receive Loopback Deactivation Code Register - Code 0 RLDCR0 0x0127

Defect Detection Enable Register DDER 0x0129

Loopback Code Control Register - Code 1 LCCR1 0x012A

Receive Loopback Activation Code Register - Code 1 RLACR1 0x012B

Receive Loopback Deactivation Code Register - Code 1 RLDCR1 0x012C

Loopback Code Control Register - Code 2 LCCR2 0x012D

Receive Loopback Activation Code Register - Code 2 RLACR2 0x012E

Receive Loopback Deactivation Code Register - Code 2 RLDCR2 0x012F

Reserved - E1 mode only - 0x0130 - 0x013F

Transmit SPRM and NPRM Control Register TSPRMCR 0x0142

Data Link Control Register 2 DLCR2 0x0143

Transmit Data Link Byte Count Register 2 TDLBCR2 0x0144

Receive Data Link Byte Count Register 2 RDLBCR2 0x0145

Data Link Control Register 3 DLCR3 0x0153

Transmit Data Link Byte Count Register 3 TDLBCR3 0x0154

Receive Data Link Byte Count Register 3 RDLBCR3 0x0155

BERT Control Register BCR 0x0163

SSM BOC Control Register BOCCR 0x0170

SSM Receive FDL Register RFDLR 0x0171

SSM Receive FDL Match 1 Register RFDLMR1 0x0172

SSM Receive FDL Match 2 Register RFDLMR2 0x0173

SSM Receive FDL Match 3 Register RFDLMR3 0x0174

SSM Transmit FDL Register TFDLR 0x0175

SSM Transmit Byte Count Register TBCR 0x0176

Device ID Register DEVID 0x01FE

Revision Number Register REVID 0x01FF

Time Slot (payload) Control (0x0300 - 0x03FF)

Transmit Channel Control Register 0-23 TCCR 0-23 0x0300 - 0x0317

Transmit User Code Register 0-23 TUCR 0-23 0x0320 - 0x0337

ABLE

1: R

EGISTER

UMMARY

UNCTION

YMBOL

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