Anaya Tech Systems ezTrainer Manuel utilisateur
ezTrainer
User Manual
FPGA MADE eAzY
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ezTrainer FPGA Kit
User Manual Rev 1.0
ezTrainer
FGPAs made EAZY
User Manual
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Anaya Tech Systems Pvt Ltd
1.0 INTRODUCTION
Thanks for your support to help Anaya Tech Systems bring quality FPGA systems to you. The ezTrainer kit is a
valuable FPGA learning platform and helps you realize your digital and FPGA learning potentials.
1.1 KNOW YOUR BOARD
This kit comes to you along with all the required paraphernalia to help you kick start your FPGA designs. Here’s
a snap shot of the board, explaining the interfaces that you see:
Along with the board, you should have received:
- A 5V DC adapter to power the board (the board can also be USB powered)
- UART cable
- Ethernet cable
- USB cable
- A CD that contains our SW and the reference documents, along with some demo application codes.
VGA out
UART
MIC IN
SPK OUT
ETHERNET
USB
5V Adapter Input
Power Switch Reset Button
32 pin General
Purpose Header
LCD
Xilinx Spartan-3E
XC3S250E
Power, Done and
General Purpose LEDs
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As can be seen the board has been uniquely designed to:
- Help you learn basic and advanced digital design.
- Introduce technologies like USB, Ethernet, Audio etc. which are the most sought after in the industry today
- Learn Embedded design basics with flash, SDRAM and UART present on board.
- Port your DSP/multimedia applications with the FPGA supporting 250 K system gate, 12 Multipliers and 4
DCMs.
- Lets you interface you own “Custom” PCBs, general purpose boards to the 32 pin General purpose header
- The ezConnect SW lets you download your bit files to the FPGA without the need for a separate expensive
JTAG cable.
- Demo applications help you have a hands on to develop your own programs.
- The board is also available with a higher density option of XC3S500E, contact sales for details.
1.2 MAIN COMPONENTS
The board has the following main components:
• FPGA - Xilinx Spartan-3E XC3S250E, 208 pin PQFP package
• SPI Flash 8 Mbit - ST Microelectronics M25P80-VMW6
• SDRAM 128 Mbit - ISSI IS42S16800E
• USB Transceiver - FTDI FT2232H
• UART Transceiver - Maxim IX MAX3221
• Mono Audio Codec - TI TLV320AIC1106
• 10/100 Mbps Ethernet PHY - KSZ8041TL
• 16X2 character LCD Screen
• GPIO header that supports 15 differential pair or 32 single ended signals. Also contains VDD (3.3V) and
GND pins to help you power your custom PCBs
• The main design tool, XIlinx ISE (webpack edition), can be downloaded free of cost from www.xilinx.com.
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2.0 POWERING UP
The board can be powered up from a wall adapter with a DC output of 5V/1A. The adapter should have a center
pin of power +5V and outer part ground 0V. See below:
If you have the UART cable connected, a serial terminal shows up once the FPGA is loaded by the default
program present in the SPI flash. See the UART section for more details.
Optionally, the board can be powered up through USB. Change the jumper position JP200 (located to the left of
the power switch) to 2-3 to power up from USB. However, it is advisable that you power the board from the DC
wall adapter.
Green color LED200 indicates a successful power on.
Plug the adapter
cable here
Push switch left to power on
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3.0 CLOCKS
The board has a 50 MHz clock oscillator fed to the pin 83 (Global Clock 3) of the FPGA. This can act as a
primary input for all your programs. A secondary clock can also be fed from the general purpose header pin 95
to the pin 80 (Global Clock 0) of the FPGA.
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4.0 CONFIGURATION OPTIONS
The FPGA can be programmed by TWO different methods:
4.1 DIRECT JTAG PROGRAMMING
All FPGAs on the market today support the standard JTAG interface for downloading a bit image file. You can
program the FPGA through our ezConnect software. Check for the following jumper settings before proceeding:
Jumpers shown in the figure JP400/401/402/403 should all be connected with pin 2 shorted to pin 3 (default
option given when the boards are shipped). Connect the USB cable and power on the board.
The JTAG configuration window of the software ezConnect is shown below. The software allows you to
download files in ________ and ________ formats:
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You can still use traditional JTAG cable to program the FPGA through the connector J305, see figures below for
pin details and location of J305
4.2 SPI PROGRAMMING
The board comes loaded with a default program in the SPI flash that can load the FPGA to run some test pro-
grams. However, ezConnect allows you to modify this flash and store your own programs. Note that the settings
for this should be the shorting of pins 1-2 on jumpers JP400/401/402/403. Also, you need to remove the default
jumpers present on J400 that short pins 1-2 and 3-4. See in the figure below. Once jumpers are removed, con-
nect the USB cable and power on the board
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The SPI configuration window of ezConnect is shown below:
Once the flash is programmed, you can remove jumpers from JP400/401/402/403. Put the jumpers back on
J400. Power up the board, and FPGA should now come up with your new image.
4.3 DONE PIN LED
Once the FPGA is programmed, a successful programming is indicated by the DONE pin going high. This is
indicated by LED400 on the board getting ON. All LEDs are located on the right of the board. See below:
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5.0 INTERFACE DETAILS
Sections below describe all interfaces of the FPGA in detail:
5.1 USB INTERFACE
A USB device FT2232H from FTDI provides the following functionalities on board
• helps to program the FPGA through JTAG
• helps to program the SPI flash on board
• Helps to download files into the on-board SDRAM (we provide sample code for this, or you can develop your
own codes)
Datasheet of this device is available on www.ftdichip.com. Table below describes the FPGA pin connections
made to this device to enhance your own development needs
5.2 SPI FLASH INTERFACE
A serial SPI flash of 8 Mbit is connected to the FPGA pins as shown in the table below. Datasheet of the flash
can be obtained from www.st.com.
Table 1:
Signal Names (as in FT2232) FPGA Pin FT2232H pin
D0 74 16
D1 75 17
D2 76 18
D3 77 19
D4 78 21
D5 89 22
D6 90 23
D7 93 24
RXF 91 26
TXE 94 27
RD 96 28
WR 97 29
SIWUA 98 30
CLKO 82 (GCLK2) 32
OE 60 33
Table 2:
Signal Names FPGA Pin M25P80 pin
SPI_DO 61 5
SPI_SK 103 6
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5.3 SDRAM INTERFACE
A 16-bit SDRAM of 128 Mbits is connected to the FPGA pins as shown in the table below. See datasheet of the
SDRAM at www.issi.com.
SPI_CS 55 1
SPI_DI 87 2
Table 3:
Signal Names FPGA Pin SDRAM pin
D0 25 2
D1 24 4
D2 23 5
D3 22 7
D4 19 8
D5 18 10
D6 16 11
D7 15 13
D8 12 42
D9 11 44
D10 9 45
D11 8 47
D12 5 48
D13 4 50
D14 3 51
D15 2 53
A0 69 23
A1 68 24
A2 65 25
A3 64 26
A4 63 29
A5 62 30
A6 50 31
A7 49 32
A8 48 33
A9 47 34
A10 45 22
Table 2:
Signal Names FPGA Pin M25P80 pin
Table des matières
