Zenith H-100 Manuel utilisateur

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H/Z-IOO

COMPUTER

SERVICE

DATA

MANUALj

ADDITIONAL

AND

UPDATE

MATERIAL

DIRECTIONS:

REPLACE the following pages with the accompanying

updated pages:

Pages 3-21 through 3-28,

Pages 3-67/3-68,

Pages 3-141 through 3-144,

First

two

pages

Section 5, Disk

Controller

and

Drives.

ADD

Part

to Section 5. This

new

data

for

the

H-207

Floppy Disk

Controller

Board.

CHANGE

the following:

Page

2-99,

Parts

Required,

Part

number

the

programming

plug

...

from:

969-18

to:

432-1168.

Page

3-159, Connectors

and

Sockets,

Part

number

the

4-pin

right-angle

connector

...

from:

432-363 to

434-363.

UPDATE

the Motherboard schematics

(refer

to the enclosed

schematic

revision

sheet)

10/82

::::}U:U~

..................

INITIAL

SETUP

INTRODUCTION

The

H/Z-100

easy

disassemble;

even

all-in-one

unit

requires

only

about

minutes

remove

the

motherboard.

However,

due

the

way

the

unit

packaged,

there

are

very

few

test

points

that

you

can

reach

while

the

unit

assembled

and

operating.

get

around

this,

you

should

build

the

following

extender

cables.

These

extender

cables

allow

you

spread

out

the

H/Z-100

over

29"

x46"

surface.

This

permits

you

easily

reach

every

while

the

unit

operating.

PARTS

REQUIRED

2-99

10-82

Qty.

ft.

Description

40-pin

ribbon

cable

w/connectors

34-pin

ribbon

cable

w/connectors

Small

alligator

clips

for

jumper

wire

construction

#18

stranded

wire

Large

spring

connector

10-pin

adapter

plug

10-hole

socket

shell

Programming

plug

Part

No.

134-1108

134-1025

260-16

344-155

432-753

432-788

432-1061

HE-432-1168

10-82

TEST,

Test

Input:

This

input

examined

by-t"ti'e"wait-for

test"

software

instruction.

low,

execution

continues,

otherwise

the

processor

waits

idle

state.

MN/MX,

Minimum/Maximum:

Logic

one

this

the

8088

the

minimun

mode,

the

mode

used

the

H/Z-100.

When

placed

the

maximum

mode,

some

the

functions

change.

Usually,

the

maximlDll

mode

used

for

larger

systems

and

multi-processing

systems.

RESET,

Reset:

Goes

high

reset

the

8088.

The

interrupts

are

disabled,

certain

registers

the

8088

are

set

cleared,

and

the

instruction

pointer

(program

counter)

points

the

memory

address

bytes

below

the

top

end

the

megabyte

range

(FFFFOH).

This

line

asserted

when

the

RESET

line

U236-11

pull

low.

igger

shape

this

signal

and

the

clock

circuits

retimes

before

applying

the

8088.

READY,

Ready:

This

acknowledgement

signal

from

the

addressed

memory

I/O

port

that

ready

transfer

data.

When

this

line

low,

the

CPU

goes

into

wait

state

until

the

addressed

device

brings

high.

This

allows

using

the

8088

with

slow

memory

I/O

dev

ices.

The

READY

signal

generated

when

U205-9

places

logic

one

U236-4.

U236

synchronizes

this

signal

with

the

8088

clock

ensure

correct

set

and

hold

times.

eLK,

8088

Clock

Input.

Five-megahertz

clock

provide

timing

the

8088.

This

signal

comes

from

U236-8

which

derives

from

the

15-MHz

crystal

Y103.

Duty

cycle

about

33i

for

optimized

timing

inside

the

8088.

When

the

8088

the

active

processor,

this

line

also

goes

the

processor

swap

port

886

provide

system

timing.

3-21

3-22

IML

51lL

Sllf~IHT

ISWAP

PORTI

"'01""*-+"'l

LIIl4Cll.O

"'-h;,q-~"

+--tt!.)~A:-;-L';.;;JT;--tI!P

•

""'04.

~---,P--st

~-----'~~,....,U.,.,2~OJ

lS'"

44J''''

......

-----------=

....

'<.ItI-L-D._('7'(I

MOL'·

1111.

••

........

+-F~

r--------------------------:~

.......

~----~II.I>

IlEF·

IW"

PROCESSOR

SWAP

PORT

(MBl)

10-82

PROCESSOR

SWAP

PORT

OVERVIEW

The

processor

swap

port

controls

which

CPU

active,

handles

interrupt

routing,

and

ensures

proper

timing

the

clock

circuits

during

the

swap.

access

the

swap

port,

the

CPU

writes

control

byte

port

OFEH.

Only

three

bits

the

byte

are

used:

ADO

controls

the

interrupt

mask,

ADl

controls

the

swap

interrupt

line,

and

AD7

performs

the

processor

swap.

PROCESSOR

SWAP

Refer

schematic

MBl

you

read

the

following.

power

up,

the

reset

circuits

clear

U171-9

logic

zero.

This

pin,

8SEL,

connects

U186-5,

a12H6

PAL.

This

responds

placing

logic

zero

U181-12

and

l~c

one

U181-2.

the

first

positive

transition

85~,

the

85HOLD

line

will

low,

enabling

the

8085

CPU.

the

first

positive

transition

the

88HOLD

line

will

high,

disabling

the

8088

cpu.

The

8085,

while

executing

the

code

the

monitor

ROM,

soon

transfers

control

the

8088.

does

this

setting

bit

the

processor

swap

port

control

byte

logic

one.

Here's

how

.•.

The

CPU

addresses

port

OFEH

assert

SWAPCS

(from

the

1/0

decoder)

U206-5.

then

sets

AD7

logic

one

U111-12.

Finally,

asserts

the

write

line

U206-6.

result,

Ul11-11

goes

high

and

latches

U171-9

logic

one.

The

8SEL

line

now

asserted.

The

values

U172-12

and U172-2

are

also

latched

their

respective

outputs,

but

these

will

covered

later.

3-23

3-24

The

8SEL

line.

now

logic

one.

causes

U186-13

change

logic

one.

U186-18

change

logic

zero.

and

U186-16

change

logic

one.

The

HOLD.

line

U185-11

asserts

whenever a

board

the

S-100

bus

takes

control

the

H/Z-100.

This

causes

U186

disable

both

the

8085

and

the

8088

through

U187. Both

CPUs

respond

returning

their

hold-acknowledge

signals;

the

8088

U186-3

and

the

8085

U171-2.

When

this

happens.

U186

asserts

the

HAK

line

17.

This,

turn,

raises

the

S-100

pHLOA

line

logic

one

U180-9.

The

board

that

generated

the

HOLD·

request

can

now

take

control

the

H/Z-100.

SWAP

TIMING

The 88SEL

line

also

goes

U188-4,

quad

D-type

latch.

This

circuit

designed

suppress

any

glitches

the

system

clock

line

when

the

H/Z-100

switches

from one

CPU

the

other.

also

ensures

that

the

CPU

being

disabled

longer

active

when

the

other

CPU

enabled.

The

8085

and

the

8088

run

separate

crystal-controlled

clocks;

the

8085 from

Y101

and

the

8088 from Y103.

Although

these

clocks

are

stable.

they

aren't

phase.

Switching

from

one

clock

another

can

cause

glitch

the

system

clock

line,

S~.

which

can

upset

the

timing

other

circuits.

3-25

10-82

SWITCHING

FROM

8085

8088

3-26

see

how

U188 and

its

associated

circuits

block

this

spike,

refer

the

waveforms on

the

page.

The two

top

waveforms

are

the

respective

clocks

for

the

8085

and

8088

CPUs.

These

are

present

the

inputs

inverters

U200-2

and

U200-14.

Assuming

that

the

8085

the

active

processor,

then

U200-1

low

and

85'

couples

through

the

inverter

form

Sl.

also

couples

through

U225B

clock

U188.

time

T1,

the

8088

selected;

the

88SEL

line

goes

logic

one

shown

the

waveforms

illustration.

The

clock

pulse

U188-9

latches

this

logic

one

into

U188-2,

the

output

The

clock

pulse

causes

the

output

latch

high,

shown

This

tri-states

U200

through

the

exclusive-DR

gate

U203B. At

the

same

time,

goes

low

couple

the

88~

clock

the

line.

Since,

this

example,

the

two

clocks

are

nearly

l80-degrees

out

phase,

the

clock

immediately

returns

zero,

causing

the

spike

the

waveforms

illustration.

until

this

time,

the

output

U203-8,

another

exclusive-

gate,

has

been

logic

one.

This

because

its

inputs

and

U188

have

been

opposite

states.

However,

since

went

low

time

T3,

both

inputs

U203C

are

the

same,

causing

U203-8

logic

zero

(waveform

E).

This

forces

the

system

clock

output

U225-3

logic

one

until

time

(waveform

F).

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