Xilinx T1 Manuel utilisateur
T1 Telco Accelerator Card
Installaon Guide
UG1518 (v1.0) December 17, 2021
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Table of Contents
Chapter 1: Introduction.............................................................................................. 4
Minimum System Requirements and Setup............................................................................ 5
Configuring the PCIe Slot Bifurcation.......................................................................................6
Chapter 2: Card Information and Installation............................................. 11
Safety Instructions.................................................................................................................... 11
Electrostatic Discharge............................................................................................................. 11
Before You Begin.......................................................................................................................11
Installing the Card.....................................................................................................................12
Chapter 3: Installing Additional Software......................................................13
Chapter 4: T1 Factory Installed Image..............................................................14
Flashing the Images in QSPI Using flash_app....................................................................... 14
Chapter 5: T1 Skeleton Design...............................................................................16
T1 Skeleton Design on the ZU19 Zynq UltraScale+ MPSoC.................................................. 16
T1 Skeleton Design on the ZU21 Zynq UltraScale+ RFSoC................................................... 17
T1 Skeleton Design Package.................................................................................................... 18
Chapter 6: Running the Tests.................................................................................20
100G Internal Connection between Zynq UltraScale+ MPSoC and
Zynq UltraScale+ RFSoC....................................................................................................... 21
2 x 25G External SFP Test......................................................................................................... 23
ZU19 Zynq UltraScale+ MPSoC PCIe Loopback Test..............................................................25
ZU21 Zynq UltraScale+ RFSoC PCIe Loopback Test...............................................................27
DDR Read/Write Tests...............................................................................................................29
Test Application Guide and Address Map.............................................................................. 32
Chapter 7: Next Steps.................................................................................................33
Chapter 8: Dependencies/Known Issues.........................................................34
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Appendix A: Programming the Devices Using JTAG.................................. 35
Flashing the Images to ZU19 Zynq UltraScale+ MPSoC QSPI Using SDK........................... 38
Flashing the Images to ZU21 Zynq UltraScale+ RFSoC QSPI Using SDK............................ 40
Programming the Bitstreams Directly ...................................................................................41
Appendix B: Regulatory Compliance Statements...................................... 43
FCC Class A Products.................................................................................................................43
Safety.......................................................................................................................................... 43
EMC Compliance........................................................................................................................44
FCC Class A User Information..................................................................................................44
VCCI Class A Statement............................................................................................................ 45
Appendix C: Additional Resources and Legal Notices............................. 46
Xilinx Resources.........................................................................................................................46
Documentation Navigator and Design Hubs.........................................................................46
Revision History.........................................................................................................................46
Please Read: Important Legal Notices................................................................................... 47
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Chapter 1
Introduction
This document provides hardware and soware installaon procedures for the T1 Telco
accelerator card along with a guide to the T1 skeleton design. The skeleton design is created
specically for the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices on
the T1 card, and provides connecons and soware to validate the main interfaces of the board.
Figure 1: T1 Telco Accelerator Card
The Xilinx® T1 Telco accelerator card is a PCI Express® (PCIe) Gen3 x16 compliant card featuring
the 16 nm Zynq® UltraScale+™ MPSoC and Zynq UltraScale+ RFSoC devices. The T1 form factor
is full height, half length (FHHL) and single slot, with a PCIe Gen 3 x16 interface that is x8x8
bifurcated providing x8 links from the host to each MPSoC and RFSoC device. Target applicaons
for the T1 card include:
• O-RAN fronthaul terminaon
• 4G LTE and 5G NR high-PHY lookaside acceleraon (supporng 3GPP split opon 7-2x)
• 5G layer 1 (L1) high-PHY lookaside acceleraon
Chapter 1: Introduction
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•Oponal use of fronthaul ports for a midhaul (F1) interface between distributed and
centralized units (DU and CU)
• 4G LTE and 5G NR inline acceleraon of L1 funcons (supporng 3GPP split opon 7-2x) for
up to 4TRX
The T1 card turns a standard server into a virtual baseband unit with the performance, low
latency, and power eciency needed for O-RAN 5G deployments. The turnkey soluon enables
operators, system integrators, and OEMs to get to market quickly and to simplify the deployment
of services at the edge.
Minimum System Requirements and Setup
The minimum system requirements for running a T1 Telco accelerator card are shown below:
Table 1: Minimum System Requirements
Component Requirement
Motherboard PCI Express 3.0 compatible with one dual-width x16 slot.
System power supply 75W through a PCI Express slot connection
Operating system Linux, 64-bit:
CentOS 7 and 8
Ubuntu 16, 18, and 20
System memory and CPU cores For deployment installations, a minimum of 16 GB plus
application memory requirements is required. For
development installations, a minimum of 64 GB of device
memory is required, but 80 GB is recommended.
A minimum of 16 logical cores is required.
Internet connection Required for downloading drivers and utilities.
Hard disk space Satisfy the minimum system requirements for your
operating system.
Auxiliary power supply No auxiliary power supply is required because the T1 card
cannot boot standalone.
Vitis™ application acceleration development flow The Vitis™ application acceleration development flow is not
currently supported.
The T1 Telco accelerator card is intended for deployment on most servers. Currently, thermal
tesng has been conducted on a Dell R640, and funconal tesng on a number of addional
servers including Dell R730 and R740.
Chapter 1: Introduction
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Configuring the PCIe Slot Bifurcation
Perform the following steps to enable bifurcaon in the slot where the T1 card has been
inserted. This is required for the T1 card to work properly.
Note: These steps are for a single T1 card deployment.
1. Power on the server. The output on the monitor is shown below.
2. Wait unl the monitor lists the shortcut keys, so you can navigate into the setup. The screen
with the shortcut keys looks like the following gure.
Chapter 1: Introduction
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3. Press F2 to open the system setup sengs.
4. In the System Setup screen, select the System BIOS opon as shown below.
5. Select Integrated Devices.
6. In the menu that is displayed, scroll down unl you get to Slot Bifurcaon. It is on the second
half of the page.
Chapter 1: Introduction
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7. Click the required slot to change bifurcaon.
8. Click Default Bifurcaon and select x8x8 or x8 Bifurcaon. This enables the T1 card in the
slot with the correct communicaon over the PCI. Click the Back buon in the lower right
hand side of the screen.
Chapter 1: Introduction
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9. Return to the System BIOS screen and click the Back buon again.
10. In the System BIOS Sengs main menu screen, click Finish.
11. A popup window will show a warning, as shown below. Click Yes to save the changes you
made.
12. Click the Finish buon again.
13. When the system has rebooted, check to see if the T1 card has been detected using the
lspci | grep Xilinx command. If the card has been detected, the response should look
like the following gure.
Chapter 1: Introduction
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