Texas Instruments TPA3120D2 Manuel utilisateur

FEATURES

DESCRIPTION

APPLICATIONS

1 Fm

Mute Control

PVCCL

TPA3120D2

SIMPLIFIED APPLICATION CIRCUIT

PVCCR

VCLAMP

GAIN1

BYPASS

1 Fm

0.22 Fm

AGND

Left Channel

Right Channel

10 V to 30 V

}

4-Step Gain

Control

Shutdown

Control

LIN

RIN

BSR

BSL

PGNDR

PGNDL

0.22 Fm

22 Hm

0.68 Fm

470 Fm

0.68 Fm

1 Fm

470 Fm

GAIN0

AVCC

MUTE

ROUT

LOUT

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007www.ti.com

25-W STEREO CLASS-D AUDIO POWER AMPLIFIER

•25-W/ch into a 4- ΩLoad from a 27-V Supply•20-W/ch into a 4- ΩLoad from a 24-V Supply

The TPA3120D2 is a 25-W (per channel) efficient,Class-D audio power amplifier for driving stereo•Operates from 10 V to 30 V

speakers in a single-ended configuration or a mono•Efficient Class-D Operation Eliminates Need

bridge-tied speaker. The TPA3120D2 can drivefor Heat Sinks

stereo speakers as low as 4 Ω. The efficiency of the•Four Selectable, Fixed-Gain Settings TPA3120D2 eliminates the need for an external heatsink when playing music.•Internal Oscillator (No External ComponentsRequired)

The gain of the amplifier is controlled by two gainselect pins. The gain selections are 20, 26, 32,•Single-Ended Analog Inputs

36 dB.•Thermal and Short-Circuit Protection With

The patented start-up and shut-down sequencesAuto Recovery

minimize pop noise in the speakers without additional•Space-Saving Surface-Mount 24-Pin TSSOP

circuitry.Package

•Televisions

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2System Two, Audio Precision are trademarks of Audio Precision, Inc.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

www.ti.com

PVCCL

MUTE

LIN

RIN

BYPASS

AGND

PVCCR

VCLAMP

PVCCR

PGNDL

LOUT

BSL

AVCC

GAIN0

GAIN1

BSR

ROUT

PGNDR

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

PWP (TSSOP) PACKAGE

(TOP VIEW)

Table 1. TERMINAL FUNCTIONS

TERMINAL

I/O/P DESCRIPTION24-PINNAME

(PWP)

Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance toSD 2 I

AVCCRIN 6 I Audio input for right channelLIN 5 I Audio input for left channelGAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCCGAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCCMute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =MUTE 4 I

outputs enabled). TTL logic levels with compliance to AVCCBSL 21 I/O Bootstrap I/O for left channelPVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCCLOUT 22 O Class-D 1/2-H-bridge positive output for left channelPGNDL 23, 24 P Power ground for left-channel H-bridgeVCLAMP 11 P Internally generated voltage supply for bootstrap capacitorsBSR 16 I/O Bootstrap I/O for right channelROUT 15 O Class-D 1/2-H-bridge negative output for right channelPGNDR 13, 14 P Power ground for right-channel H-bridge.PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCCAGND 9 P Analog ground for digital/analog cells in coreAGND 8 P Analog ground for analog cells in coreReference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time viaBYPASS 7 O

external capacitor sizing.AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCLConnect to ground. Thermal pad should be soldered down on all applications to secure theThermal pad Die pad P

device properly to the printed wiring board.

Product Folder Link(s): TPA3120D2

www.ti.com

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE UNIT

Supply voltage AVCC, PVCC – 0.3 to 36 VV

Logic input voltage SD, MUTE, GAIN0, GAIN1 – 0.3 to V

+ 0.3 VV

Analog input voltage RIN, LIN – 0.3 to 7 VContinuous total power dissipation See Dissipation Ratings tableT

Operating free-air temperature range – 40 to 85 °CT

Operating junction temperature range – 40 to 150 °CT

stg

Storage temperature range – 65 to 150 °CR

Load resistance (minimum value) 3.2 Ω

Human-body model (all pins) ± 2 kVESD Electrostatic Discharge

Charged-device model (all

± 500 Vpins)

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operations of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

PACKAGE

(1) (2)

≤25 °C DERATING FACTOR T

= 70 °C T

= 85 °C

24-pin TSSOP 4.16 W 33.3 mW/ °C 2.67 W 2.16 W

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad mustbe soldered to a thermal land on the printed-circuit board. See the PowerPAD Thermally Enhanced Package application note(SLMA002 ).

MIN MAX UNIT

Supply voltage PVCC, AVCC 10 30 VV

High-level input voltage SD, MUTE, GAIN0, GAIN1 2 VV

Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 VSD, V

= V

, V

= 30 V 125I

High-level input current MUTE, V

= V

, V

= 30 V 125 μAGAIN0, GAIN1, V

= V

, V

= 24 V 125SD, V

= 0, V

= 30 V 1I

Low-level input current MUTE, V

= 0 V, V

= 30 V 1 μAGAIN0, GAIN1, V

= 0 V, V

= 24 V 1T

Operating free-air temperature – 40 85 °C

Product Folder Link(s): TPA3120D2

www.ti.com

DC CHARACTERISTICS

AC CHARACTERISTICS

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

= 25 °C, V

= 24 V, R

= 4 Ω(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Class-D output offset voltage| V

| (measured differentially in BTL V

= 0 V, A

= 36 dB 7.5 50 mVmode as shown in Fig 30)V

(BYPASS)

Bypass output voltage No load AVCC/8 VI

CC(q)

Quiescent supply current SD = 2 V, MUTE = 0 V, No load 23 37 mAI

CC(q)

Quiescent supply current in

MUTE = 0.8 V, No load 23 mAmute modeI

CC(q)

Quiescent supply current in

SD = 0.8 V , No load 0.39 1 mAshutdown moder

DS(on)

Drain-source on-state

200 m Ωresistance

GAIN0 = 0.8 V 18 20 22GAIN1 = 0.8 V

GAIN0 = 2 V 24 26 28G Gain dBGAIN0 = 0.8 V 30 32 34GAIN = 2 V

GAIN0 = 2 V 34 36 38Mute Attenuation V

= 1Vrms – 82 dB

= 25 °C, V

= 24 V, R

= 4 Ω(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 24, V

ripple

= 200 mV

100 Hz – 48ksvr Supply ripple rejection dBGain = 20 dB

1 kHz – 52V

= 24 V, R

= 4 Ω, f = 1 kHz 16Output power at 1% THD+N

= 24 V, R

= 8 Ω, f = 1 kHz 8P

= 24 V, R

= 4 Ω, f = 1 kHz 20Output power at 10% THD+N

= 24 V, R

= 8 Ω, f = 1 kHz 10R

= 4 Ω, f = 1 kHz, P

= 10 W 0.08%Total harmonic distortion +THD+N

noise

= 8 Ω, f = 1 kHz, P

= 5 W 0.08%

85 μV20 Hz to 22 kHz, A-weighted filter,V

Output integrated noise floor

Gain = 20 dB

– 80 dBVCrosstalk P

= 1 W, f = 1 kHz; Gain = 20 dB – 60 dBMax output at THD+N < 1%, f = 1 kHz,SNR Signal-to-noise ratio 99 dBGain = 20 dBThermal trip point 150 °CThermal hysteresis 30 °Cf

OSC

Oscillator frequency 230 250 270 kHz

Product Folder Link(s): TPA3120D2

www.ti.com

FUNCTIONAL BLOCK DIAGRAM

OSC/RAMP

MUTE

CONTROL

BYPASS

CONTROL

BIAS

THERMAL

DETECT

AVDD

AVCC

LIN

RIN

MUTE

BYPASS

GAIN1

GAIN0

BSL

PVCCL

LOUT

PGNDL

VCLAMP

BSR

PVCCR

ROUT

PGNDR

VCLAMP

AVDD

AVDD/2

AVDD

AVDD/2

REGULATOR

FUNCTIONAL BLOCK DIAGRAM

AGND

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

Product Folder Link(s): TPA3120D2

www.ti.com

TYPICAL CHARACTERISTICS

f − Frequency − Hz

20 100 1k 10k

THD+N Total Harmonic Distortion + Noise %

0.1

20k

0.01

V = 18 V

R = 4 (SE)

Gain = 20 dB

P = 5 W

P = 2.5 W

P = 1 W

f − Frequency − Hz

20 100 1k 10k

THD+N Total Harmonic Distortion + Noise %

0.1

20k

0.01

V = 24 V

R = 4 (SE)

Gain = 20 dB

P = 10 W

P = 1 W

P = 5 W

f − Frequency − Hz

20 100 1k 10k

THD+N Total Harmonic Distortion + Noise %

0.1

20k

0.01

V = 24 V

R = 8 (SE)

Gain = 20 dB

P = 1 W

P = 2.5 W

P = 5 W

P − Output Power − W

10 m 100 m 1 10

THD+N Total Harmonic Distortion + Noise %

0.01

0.1

V = 12 V

V = 24 V

V = 18 V

R = 4 (SE)

Gain = 20 dB

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

All tests are made at frequency = 1 kHz unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY FREQUENCY

Figure 1. Figure 2.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY OUTPUT POWER

Figure 3. Figure 4.

Product Folder Link(s): TPA3120D2

www.ti.com

THD+N - Total Harmonic Distortion + Noise - %

P − Output Power − W

R = 8 (SE)

Gain = 20 dB

0.01

0.1

10 m 100 m 1 10 40

V = 12 V

V = 24 V

V = 18 V

-100

20 100 1 k 20k

f − Frequency − Hz

Crosstalk dB

10k

-90

-80

-70

-60

-50

-40

-30

-20

-10

R to L

L to R

V = 18 V

V = 1 Vrms

R = 4 (SE)

Gain = 20 dB

-300

200

-200

-100

100

20 100k100 200 1k 2k 10k 20k

f − Frequency − Hz

Gain dB

Phase -o

Gain

Phase

V = 24 V

R = 4 (SE)

Gain = 20 dB

L = 33 H

C = 1 F

C = 470 F

filt

-10020 100 1 k 20k

f − Frequency − Hz

10k

-90

-80

-70

-60

-50

-40

-30

-20

-10

Crosstalk dB

L to R

R to L

V = 18 V,

V = 1 V,

R = 8 ,

Gain = 20 dB

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE CROSSTALKvs vsOUTPUT POWER FREQUENCY

Figure 5. Figure 6.

CROSSTALK GAIN/PHASEvs vsFREQUENCY FREQUENCY

Figure 7. Figure 8.

Product Folder Link(s): TPA3120D2

www.ti.com

-250

200

-200

-150

-100

-50

100

150

22.5

7.5

12.5

17.5

20 100k100 200 1k 2k 10k 20k

f − Frequency − Hz

Gain dB

Phase -o

Gain

Phase

V = 24 V

R = 8 (SE)

Gain = 20 dB

L = 47 H

C = 0.22 F

C = 470 F

filt

V − Supply Voltage − V

16 26

POutput Power W

O--

THD = 10%

THD = 1%

R = 4 (SE)

Gain = 20 dB

1210 14 18 20 22 24 28

THD = 10%

THD = 1%

V - Supply Voltage - V

P - Output Power - W

R = 8 (SE)

Gain = 20 dB

16 26 301210

14 18 20 22 24 28

P − Output Power − W

6 16

Efficiency %

100

12 V

18 V 24 V

R = 4 (SE)

Gain = 20 dB

20 4 8 10 12 14 18

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.

GAIN/PHASE OUTPUT POWERvs vsFREQUENCY SUPPLY VOLTAGE

Figure 9.

A. Dashed line represents thermally limitedregion.

Figure 10.

OUTPUT POWER EFFICIENCYvs vsSUPPLY VOLTAGE OUTPUT POWER

Figure 11. Figure 12.

Product Folder Link(s): TPA3120D2

www.ti.com

P − Output Power − W

Efficiency %

100

0 1 2 3 4 5 6 7 8 9

10 11

R = 8 (SE)

Gain = 20 dB

12 V 18 V 24 V

P − Output Power − W

I−Supply Current −A

12 32

1.6

0.2

0.6

18 V

0.8

1.2

0.4

1.4

1.8

40 8 16 20 24 28 36

R = 4 (SE)

Gain = 20 dB

24 V

12 V

-120

20 100 1 k 20k

f − Frequency − Hz

Power Supply Rejection Ratio dB

10k

-110

-100

-90

-80

-70

-50

V = 24 V

V = 0.2 V

R = 4 (SE)

Gain = 20 dB

O(ripple) PP

-40

-30

-20

-10

-60

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25

P - Output Power - W

I - Supply Current - A

12 V

18 V

24 V

R = 8 ,

Gain = 20 dB

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.

EFFICIENCY SUPPLY CURRENTvs vsOUTPUT POWER OUTPUT POWER

Figure 13. Figure 14.

SUPPLY CURRENT POWER SUPPLY REJECTION RATIOvs vsOUTPUT POWER FREQUENCY

Figure 15. Figure 16.

Product Folder Link(s): TPA3120D2

www.ti.com

f − Frequency − Hz

20 100 1k 10k

THD+N Total Harmonic Distortion + Noise %

0.1

20k

0.01

0.001

V = 24 V

R = 8 (BTL)

Gain = 20 dB

P = 20 W

P = 1 W

P = 5 W

R = 8 (BTL)

Gain = 20 dB

P − Output Power − W

10 m 100 m 1 10

THD+N Total Harmonic Distortion + Noise %

0.01

0.1

V = 12 V

V = 24 V

V = 18 V

-200

400

-100

100

200

300

-30

-20

-10

20 200k100 1k 10k

f - Frequency - Hz

Phase - °

Gain - dB

Phase

Gain

V = 24 V,

R = 8 (BTL),

Gain = 20 dB,

L = 33 H,

C = 1 F

filt

V − Supply Voltage − V

16 26

POutput Power W

O--

THD = 10%

THD = 1%

R = 8 (BTL)

Gain = 20 dB

1210 14 18 20 22 24 28

TPA3120D2

SLOS507E – MARCH 2007 – REVISED SEPTEMBER 2007

TYPICAL CHARACTERISTICS (continued)All tests are made at frequency = 1 kHz unless otherwise noted.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsFREQUENCY OUTPUT POWER

Figure 17. Figure 18.

GAIN/PHASE OUTPUT POWERvs vsFREQUENCY SUPPLY VOLTAGE

Figure 19.

A. Dashed line represents thermally limitedregion.

Figure 20.

Product Folder Link(s): TPA3120D2

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