ST STNRG011A Manuel utilisateur
Introduction
This user manual provides information for developing applications with the STNRG011A digital combo multi-mode PFC and
time-shift LLC resonant controller.
The STNRG011A is a STMicroelectronics® digital device tailored for SMPS applications. It embodies a multi-mode (transition-
mode and DCM) PFC controller, a high voltage doubleended controller for the LLC resonant half-bridge, an 800 V-rated startup
generator and a sophisticated digital engine, that manages optimal operation of the three blocks.
All the key application parameter of the device are stored into an internal NVM (non-volatile memory), allowing wide
configurability and calibration.
This user manual goes in detail through all the NVM parameters and explains how to set them in a real application. For any
other information about STNRG011A product, please refer to the STNRG011A datasheet.
STNRG011A NVM parameters description
UM3002
User manual
UM3002 - Rev 1 - April 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
1Notes
1.1 Parameters packing
The parameters in the NVM are packed starting from the first one at the address 0x00, going through the
boundaries between bytes if required.
1.2 NVM configuration
The NVM is divided into 4 parts called bank0, bank1, bank2 and bank3. Each bank size is 8 bytes.
Bank0 contains mainly trimming and traceability information. For this reason, users cannot modify it.
Bank1, 2 and 3 contain the parameters described in this document. The user can modify them to adapt the
STNRG011A algorithms to his application.
1.3 GUI application
In order to easily program the NVM during the development of a new application, a graphical user interface (GUI)
has been developed. The GUI strictly works with a communication interface board and allows real time monitoring
of the device, NVM and EEPROM contents checking and programming. For more information about the GUI and
the interface board, please refer to the user manual on www.st.com: Getting started with the STEVAL-PCC020V2:
USB to I²C UART interface board and associated GUI for STNRG products.
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Notes
UM3002 - Rev 1 page 2/42
2Equations to set the parameters
2.1 PFC
2.1.1 PFC power calculation
The device uses an internal numerical representation of the power delivered. The relationship between the
internal value and the true power is as follows:
Equation 1
pinn = P L
128 ∙LSBVin2∙Tck
(1)
Where:
•pinn is the internal numerical power estimation
•P is the real power level
•L is the PFC choke inductance value
•LSBVin = 1.89 V
•Tck = 16.66 ns
Note that this relation is a loose approximation due to the PFC parasitics, which offset the true power level.
2.1.2 PFC compensation parameters
The PFC compensation is calculated at each line valley (i.e. input mains zero crossing). The device uses the
following formula to calculate the power
Equation 2
pinn = 2 ∙Kp + Ki 1
1−z−1err (2)
where err is equal to the voltage error (target output voltage - real output voltage) divided by VerrLSB = 0.473 V.
2.2 LLC
The LLC compensation is based on an analog circuitry at the secondary side.
The time shift value applied by the controller is calculated using the sampled value on the LLC_FB pin.
Equation 3
TS = 0.5 ∙VFB
LSBVFB −FBOS (3)
where:
• TS = time shift value applied to LLC SMEDs (in 60 MHz clock ticks)
• VFB = Voltage on the LLC_FB pin
• LSBVFB = 2.44 mV (used to convert the LLC_FB voltage value in the internal numerical format)
• FBos = fixed offset (68)
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Equations to set the parameters
UM3002 - Rev 1 page 3/42
3Parameters description
3.1 General system configuration
3.1.1 Shutdown feature
Size: 1 bit
Enables / disables the shutdown comparator connected to the LLC_FB pin.
Available values are:
• Disabled
• Enabled
The shutdown comparator is connected to the LLC_FB pin. Its threshold is 125 mV. If the pin is brought below this
threshold, and the comparator is enabled, the system will shut down as long as the pin's voltage remains below
the threshold.
This feature can be used to realize extra protections (e.g. OTP protection for power stage).
Use
It is suggested to disable the shutdown comparator if it is not used.
3.1.2 Patch upload from EEPROM
Size:1 bit
Enables / disables the patching feature. Available values are:
• Disabled
• Enabled
If patching is disabled the STNRG011A will not upload the patch from the external EEPROM.
Use
The default value is disabled (i.e. patching disabled). The user has to maintain the patching feature disabled if no
EEPROM is installed on the application.
3.1.3 ATE mode
Size:1 bit
Enables / disables the ATE mode. Available values are:
• Enabled
• Disabled
Use
The ATE mode is required to read/write the NVM. Therefore, this parameter should be set to “Enabled”.
In case, after the correct programming of all NVM parameters, the user wants to keep such information protected,
he can disable the ATE mode.
Warning: Once the bit will be set to disabled, it will be impossible to access the NVM.
3.1.4 System monitoring
Size:1 bit
Enables / disables the system monitoring. Available values are:
• Enabled
• Disabled
Monitoring is the periodic unidirectional communication through the UART interface used by the STNRG011A to
send out information (including the power estimation, PFC operating mode, etc.). If this feature is not requested,
the user can disable it and stop the activity on the UART interface.
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Parameters description
UM3002 - Rev 1 page 4/42
3.1.5 VAC reading improvement
Size:1 bit
Enables / disables the VAC reading improvement feature. Available values are:
• Disabled
• Enabled
If the feature is enabled, the IC will sink from the VAC pin IVAC_HV_SINK current during line synchronization at
the start-up and IXCD current for about 5 ms in case of the brown-out event, to avoid false brown-in. This allows
having a voltage on the VAC pin that has a good shape and compensate the effect of an unbalanced Y-cap in the
AC input (such unbalance generates a charge pump effect that increases the VAC voltage).
Use
It is suggested to keep the feature enabled.
3.1.6 Early warning feature
Size:1 bit
Enables / disables the early warning (EW) pulse generation. This pulse is used to manage the “Power OK” signal.
Available values are:
• Enabled
• Disabled
The EW pulse is generated on the PFC_FB pin. This pin, normally the input for sensing the PFC output voltage, in
case of device shutdown becomes an output and goes to 5 V.
The duration of the pulse depends on the shut-down cause.
For the normal shutdown (i.e. mains removal, brown-out event, OLP and PFC UVP faults) the pulse is 5 ms long
(normal pulse). During this time, the PFC is stopped while the LLC is still working keeping the output voltage
regulated.
In case of a dangerous fault, both PFC and LLC stages are immediately stopped and the EW pulse is about 270
μs long (quick pulse).
3.1.7 EW signal in burst mode
Size:1 bit
Selects the duration of the early warning pulse in the burst mode.
Available values are:
• Quick
• Normal
Use
The selection will force the system to use the quick pulse without any LLC activity in the burst mode also during
the normal shutdown. This is useful in case the LLC tank is not designed to keep the output voltage regulated at
no-load, avoiding the overshoot of the output.
3.1.8 Non latched faults timer
Size:2 bits
Sets the time between retries in the non-latched (auto restart) mode.
Available values are:
• 546 ms
• 1.09 s
• 2.18 s
• 4.37 s
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General system configuration
UM3002 - Rev 1 page 5/42
3.2 Faults parameters
3.2.1 Surge detection
Size:1 bit
Enable / disable the surge comparator.
Available values are:
• Disabled
• Enabled
The surge comparator is connected to the VAC pin and its threshold is 430 V.
3.2.2 PFC OC2 detection
Size:1 bit
Enables / disables the PFC OC2 comparator.
Available values are:
• Disabled
• Enabled
The PFC OC2 comparator is connected to the PFC_CS pin and its threshold is 900 mV.
3.2.3 Max number of PFC OC2
Size:2 bits
Sets the number of consecutive PFC OC2 events before shutting down.
Available values are:
• 1
• 2
• 4
• 8
Use
The suggested value is “2”, since it is a good compromise between the noise rejection and protection
reactiveness.
The value “1” can be used if minimum intervention time is required: in this case, pay attention because some
noise could trigger the protection. Higher values can be used in case of noisy boards (in this case, the reaction to
real OCP2 events will be slower).
3.2.4 PFC HW OVP detection
Size: 1 bit
Enable / disable the hardware PFC OVP comparator.
Available values are:
• Disabled
• Enabled
The PFC OVP comparator is the hardware protection against the bulk overvoltage. It is connected to the PFC_FB
pin and its threshold is set at 2.3 V.
The fault is always immediate and shuts down the system.
Use
It is suggested to leave the PFC OVP comparator enabled.
3.2.5 LLC OC2 detection
Size: 1 bit
Enables / disables the LLC OC2 comparator.
Available values are:
• Disabled
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Faults parameters
UM3002 - Rev 1 page 6/42
• Enabled
The LLC OC2 comparator is connected to the LLC_CS pin and its threshold is 700 mV.
3.2.6 Max number of LLC OC2
Size: 2 bits
Sets the number of consecutive LLC OC2 events before shutting down.
Available values are:
• 1
• 2
• 4
• 8
Use
The suggested value is “2”, since it is a good compromise between the noise rejection and protection
reactiveness.
The value “1” can be used if minimum intervention time is required: in this case, pay attention because some
noise could trigger the protection.
3.2.7 LLC OVP detection
Size: 1 bit
Enables / disables the LLC OVP comparator.
Available values are:
• Disabled
• Enabled
The LLC OVP comparator is connected to the LLC_AUX pin and its threshold is 2.5 V.
3.2.8 Disconnection faults detection
Size: 1 bit
Enables / disables the feedback disconnections faults detection.
Available values are:
• Disabled
• Enabled
Use
It is suggested to enable the feedback disconnection faults detection.
Note: Disconnection faults have always “latched” behavior.
3.2.9 PFC OC2 behavior
Size: 1 bit
Sets the behavior of PFC OC2 protection.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.10 PFC HW OVP behavior
Size: 1 bit
Sets the behavior of the PFC OVP.
Available values are:
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Faults parameters
UM3002 - Rev 1 page 7/42
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.11 PFC UVP behavior
Size: 1 bit
Sets the behavior of the PFC UVP.
Available values are:
• Slow
• Adaptive
When the UVP threshold is detected, if this parameter is set “Slow”, the device will shut down the power supply if
the PFC UVP is still present for at least 100 ms.
If the behavior is set to “Adaptive”, the device will shut down the power supply if the PFC UVP is triggered and the
mains voltage is detected below the brown-out threshold. If both conditions are not true, the system will manage
the fault as if the selection is set “Slow”. This selection enables large capacitive loads to be connected through
the OR-Ing FET. The “Slow” timing could be helpful in some case, when the designer would like to let the system
work with a low bulk voltage.
Please remember that, because of the LLC OC2 protection and the ACP feature, the system is still protected
against overstresses.
3.2.12 LLC SS timeout behavior
Size: 1 bit
Sets the behavior of the LLC soft-start timeout protection.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.13 LLC ACP behavior
Size: 1 bit
Sets the behavior of the LLC ACP (both “Soft” and “Hard”).
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.14 LLC OC2 behavior
Size: 1 bit
Sets the behavior of the LLC OC2 protection.
Available values are:
• Not latched
• Latched
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Faults parameters
UM3002 - Rev 1 page 8/42
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.15 LLC OLP behavior
Size: 1 bit
Sets the behavior of the LLC overload protection (OLP).
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer”.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.2.16 LLC OVP behavior
Size: 1 bit
Sets the behavior of the LLC OVP.
Available values are:
• Not latched
• Latched
If the fault is set as “Not latched” the system will try to restart after the time defined by the “Non latched faults
timer” parameter.
If the fault is set as “Latched” the switching activity will remain off and the VCC will remain between 15 V and 17 V
using the HV start-up generator (as long as there is the mains connected).
3.3 PFC parameters
3.3.1 PFC Ki
Size:3 bits
Sets the integral constant of the PFC compensation filter.
Available values are:
• 4
• 6
• 8
• 12
• 16
• 24
• 32
• 48
3.3.2 PFC Kp
Size:3 bits
Sets the proportional constant of the PFC compensation filter.
Available values are:
• 8
• 12
• 16
• 24
• 32
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PFC parameters
UM3002 - Rev 1 page 9/42
• 48
• 64
• 96
Note: The device uses 2 * Kp for calculations (see Section 2.1.2 PFC compensation parameters)
3.3.3 PFC MOSFET LEB
Size: 3 bits
Sets the PFC MOSFET minimum on-time (also called LEB, i.e. “Leading Edge Blanking”).
Available values are:
• 133 ns
• 167 ns
• 200 ns
• 233 ns
• 267 ns
• 333 ns
• 400 ns
• 467 ns
This time is used to filter the spike on the PFC_CS pin at the PFC MOSFET turn-on. During this time the PFC_CS
comparator output (THD improver) is ignored.
Use
Adjust the blanking time according to design requirements.
The middle value 267 ns can be used as a starting point and then, after looking at the PFC_CS waveform during
the PFC operation it can be adjusted.
3.3.4 PFC THD improver base
Size: 3 bits
Sets the base value for the ReCOT functionality (THD improver).
Available values are:
• 0 mV
• 2 mV
• 4 mV
• 6 mV
• 8 mV
• 10 mV
• 12 mV
• 14 mV
The parameter sets the PFC_CS comparator threshold.
Use
This parameter can be tuned to improve the THD of the system. Together with the “PFC THD improver gain”, this
parameter can be used to improve the distortion and power factor of the PFC observing the current waveform and
THD/PF measurements.
UM3002
PFC parameters
UM3002 - Rev 1 page 10/42
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