SST SST65P542R Manuel utilisateur

S74004-00-000 4/03

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SoftPartition is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Programming User’s Manual

Remote Controller

SST65P542R

Programming Reference Manual

TABLE OF CONTENTS

1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.0 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.0 PIN ASSIGNMENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4.0 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.0 MCU CORE AND INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1 Registers and Control Bit Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.1.1 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.2 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.3 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5.1.5 Processor Status Word (PSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2.1 Inherent (INH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2.2 Immediate (IMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5.2.3 Direct (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.4 Extended (EXT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.5 Indexed, No Offset (IX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.6 Indexed, 8-bit Offset (IX1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.7 Indexed, 16-bit Offset (IX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.2.8 Relative (REL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2.9 Bit Set/Clear (BSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.2.10 Bit test and branch (BTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5.3 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6.0 I/O REGISTERS DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.0 INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.0 RESETS AND CLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9.0 POWER-DOWN MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.1 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2 IDLE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SST65P542R

Programming Reference Manual

10.0 THE CORE TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10.1 Computer Operating Properly Watchdog Timer Control Register (CWTC) . . . . . . . . . . . . . . . . . . . . . 26

10.2 Timer Control and Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.1 Core Timer Overflow (CTOF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.2 Real-Time Interrupt Flag (RTIF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.3 Timer Overflow Enable (TOFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.4 Real-Time Interrupt Enable (RTIE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.5 Timer Overflow Flag Clear (TOFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.6 Real-Time Interrupt Flag Clear (RTFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.2.7 Real-Time Interrupt Rate Select (RT1-RT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.3 Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.4 COP Watchdog Timer (CWT) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.5 Timer During IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11.0 CARRIER MODULATOR TRANSMITTER (CMT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.1 Carrier Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.1.1 Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

11.1.2 Carrier Generator Data Registers (CHR1, CLR1, CHR2, and CLR2) . . . . . . . . . . . . . . . . . . . . 30

11.2 Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.2.1 Time mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

11.2.2 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11.2.3 Extended Space Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.2.4 End Of Cycle (EOC) Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.2.5 Modulator Period Data Register (MDR1, MDR2, and MDR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.0 PROGRAMMING FLOW DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

13.0 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SST65P542R

Programming Reference Manual

1.0 INTRODUCTION

The SST65P542R is a member of SST’s 8-bit, application-specific microcontroller family targeting IR remote con-

troller applications.

The SST65P542R microcontroller provides high-functionality to infrared remote controller products. The device

offers flexibility to store different remote control configurations for controlling multiple appliances. The configura-

tions are either programmed at the factory during the manufacturing process or updated through a web download

procedure using the serial interface.

Using the SuperFlash nonvolatile memory technology, the SST65P542R enhances the functionality of the conven-

tional universal remote controller devices by integrating multiple functions of a remote controller system in a single

chip solution. The built-in LED I/O ports can directly drive LED indicators. The IR transmitter port drives signals to

the infrared transmitter, which, in turn, remotely controls appliances.

The SoftPartition flash memory architecture allows seamless partition of the program code, protocol tables, and

user data in the small granularity of 128 Byte sectors. The small sector size and fast Erase/Write time greatly

increase the time and power efficiency when altering the contents of the flash memory.

The embedded controller is designed and manufactured using SST’s patented and proprietary SuperFlash EEPROM

technology.

SST’s highly reliable SuperFlash technology provides significant advantages over conventional flash memory tech-

nology. These advantages translate into significant overall cost savings and reliability benefits for customers.

PRODUCT FEATURES

• 8-bit MCU Core

– Enhanced 6502 Microprocessor Megacell

• 4 MHz Typical Oscillator Clock Frequency

• 8 MHz maximum clock frequency

• 16 KByte of user programmable flash memory

• 352 Bytes SRAM

• IR Input Pin for Learning Mode

• Power-down Modes

• Carrier Modulator Transmitter

– Supports Baseband, Pulse Length Modulator (PLM), and Frequency Shift Keying (FSK)

• Core Timer / Counter

– 14-stage multifunctional ripple counter

– Includes timer overflow, POR, RTI, and CWT

• General Registers:

– Accumulator (8-bit)

– Index Register (8-bit)

• Control registers:

– Program Counter (16-bit)

– Stack Pointer (16-bit / 6 addressable bits)

– Condition code register (8-bit)

• Addressing modes supported:

1. Immediate 3. Extended 5. Indexed, no offset 7. Indexed, 16-bit offset 9. Bit test and branch

2. Direct 4. Relative 6. Indexed, 8-bit offset 8. Bit set/clear 10. Inherent

• Data types supported:

1. Bit data (manipulation instructions)

2. Byte data

SST65P542R

Programming Reference Manual

2.0 BLOCK DIAGRAM

IRQ#

SuperFlash

EEPROM

16K x8

Interrupt

Control

MCU Core

RAM

352K x8

Port A

Port B

Timer/Counter Interrupt

IRO Carrier Modulator

Transmitter

Real-Time

Counter

Core Timer

/ Counter

4004 B2.5

COP Watchdog

Timer

Port C

FUNCTIONAL BLOCK DIAGRAM

SST65P542R

Programming Reference Manual

3.0 PIN ASSIGNMENTS

FIGURE 3-1: PIN ASSIGNMENTS FOR 28-PIN SOIC

TABLE 3-1: PIN DESCRIPTIONS

Pins Symbol Type1

1. I = Input

O = Output

Name and Functions

16-9 PA[7:0] I/O1Port A: The state of any pin in Port A is software programmable and every line is configured as

an input during any external reset.

8-1 PB[7:0] I/O with

internal

pull-ups

Port B: The state of any pin in Port B is software programmable and every line is configured as

an input during any external reset. Each I/O line contains a programmable interrupt/pull-up for

keyscan. PB[7] is used as a serial interface data line when the serial interface is enabled.

20-17 PC[3:0] I/O Port C: Every pin in Port C is a high-current pin and its state is software programmable. All lines

are configured as inputs during any external reset.

23 IRO O IRO: Suitable for driving IR LED biasing logic, the IRO pin is the high-current source and sink

output of the carrier modulator transmitter subsystem. Default state is low after any external

reset.

21 LPRST# I Low-Power Reset: An active-low pin, LPRST# function sets MCU to low-power reset mode.

The MCU, once in low-power reset mode, is held in reset with all processor clocks and crystal

oscillator halted. An internal Schmitt trigger is included in the LPRST# pin to improve noise

immunity.

24 RESET# I Reset: By setting the RESET# pin low the MCU is reset to a default state. An internal Schmitt

trigger is included in the RESET# pin to improve noise immunity.

28 OSC1 I Oscillator 1,2: These 2 pins interface with external oscillator circuits.

A crystal resonator, a ceramic resonator, or an external clock signal can be used.

27 OSC2 O

25 IRQ# I Interrupt Request: The IRQ# is negative edge-sensitive triggered. An internal Schmitt trigger

is included in the IRQ# pin to improve noise immunity.

26 VDD IPower Supply: Supply Voltage

22 VSS IGround: Circuit ground. (0V reference)

T3-1.5 4004

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PA 0

PA 1

PA 2

PA 3

PA 4

PA 5

OSC1

OSC2

VDD

IRQ#

RESET#

IRO

VSS

LPRST#

PC3

PC2

PC1

PC0

PA 7

PA 6

28-pin SOIC

4004 F10.1

SST65P542R

Programming Reference Manual

4.0 MEMORY ORGANIZATION

The SST65P542R has a total of 64 KByte of addressable memory. A memory map is shown in Figure 4-1. The

memory consists of 32 Bytes of I/O registers, 352 Bytes of SRAM, 16 KByte of user flash memory, and 128 Bytes

of user vectors.

FIGURE 4-1: MEMORY MAP

FF7FH

FF80H

BFFFH

C000H

Flash Memory

(128 sectors)

127 Sectors

(128 Bytes per sector)

User

Memory

0000H

001FH

0020H

017FH

0180H

FFFFH

4004 F11.3

I/O

Registers

352 Bytes

SRAM

User

Vector

16,256

Bytes

0180H

BFFFH

Reserved

3FF0H

FF80H

FFF4H

FFFFH

CWT

Reset

Flash Memory

Read Protection

Reset and

Interrupt

Vectors

SST65P542R

Programming Reference Manual

5.0 MCU CORE AND INSTRUCTION SET

This section provides a description of the MCU core registers, the instruction set and the addressing modes.

5.1 Registers and Control Bit Assignments

The MCU contains five registers, as shown in the programming model of Figure 5-1. The interrupt stacking order is

shown in Figure 5-2.

FIGURE 5-1: PROGRAMMING MODEL

Unused

Half Carry

Interrupt Disable

Negative

Zero

Carry

4004 F01.4

PCL PCH

0 0 0 0 0 0 0 0 1 1

ACCUMULATOR

INDEX REGISTER

PROGRAM COUNTER

STACK POINTER

PSW REGISTER 111H I NZC

SST65P542R

Programming Reference Manual

FIGURE 5-2: STACKING ORDER

Stacking decreases memory address and unstacking (Return) increases memory address.

5.1.1 Accumulator (A)

The accumulator is a general purpose 8-bit register used to hold operands and results of an arithmetic calculation

or data manipulations.

5.1.2 Index Register (X)

The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective

address. The index register may also be used as a temporary storage area.

5.1.3 Program Counter (PC)

The program counter is a 16-bit register, which contains the address of the next byte to be fetched.

5.1.4 Stack Pointer (SP)

The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an

MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location 00FFH. The stack pointer

is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When

accessing memory, the 8 most significant bits are permanently set to 00H. These eight bits are appended to the

lower 8 significant register bits to produce an address within the range of 00C0H to 00FFH. Subroutines and inter-

rupts may use up to 256 (decimal) locations. If 64 locations are exceeded, i.e. if stack pointer is pointing to 00C0H

and stacking operation carried out, the stack pointer wraps around to 00FFH and overwrites the previously stored

information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.

4004 F02.3

Unstacking increasing address

Stacking decreasing address

PSW

ACCUMULATOR (A)

INDEX REGISTER (X)

PCH

PCL

SST65P542R

Programming Reference Manual

5.1.5 Processor Status Word (PSW)

The PSW is a 5-bit register. These bits can be individually tested by a program, and specific actions can be taken

as a result of their state. Each bit is explained in the following paragraphs.

5.1.5.1 Half Carry (H)

This bit is set during ADD and ADC operations to indicate that a carry has occurred between bits 3 and 4 of the

accumulator during an ADD or ADC operation.

5.1.5.2 Interrupt (I)

When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is

latched and remains pending until the interrupt bit is cleared. After any reset, the interrupt mask is set and can be

cleared by software instruction (CLI).

5.1.5.3 Negative (N)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative.

5.1.5.4 Zero (Z)

When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.

5.1.5.5 Carry/Borrow (C)

When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last

arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.

5.2 Addressing Modes

Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The

various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling

tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instruc-

tions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute

(extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in

most applications.

Extended addressing permits jump instructions to reach all memory locations. The term ‘effective address’ (EA) is

used in describing the various addressing modes. The effective address is defined as the address from which the

argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below.

Parentheses are used to indicate ‘contents of’ the location or register referred to. For example, (PC) indicates the

contents of the location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon

indicates concatenation of two bytes.

5.2.1 Inherent (INH)

In the inherent addressing mode, all the information necessary to execute the instruction is contained in the

opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no

other arguments are included in this mode. These instructions are one byte long.

5.2.2 Immediate (IMM)

In the immediate addressing mode, the operand is contained in the byte immediately following the opcode.

EA = PC+1; PC ←PC+2

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