Silicon Laboratories Si4330 Manuel utilisateur

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si4330

Si4330 ISM RECEIVER

Features

Applications

Description

Silicon Laboratories’ Si4330 highly integrated, single chip wireless ISM receiver is

part of the EZRadioPRO™ family. The EZRadioPRO family includes a complete

line of transmitters, receivers, and transceivers allowing the RF system designer

to choose the optimal wireless part for their application.

The Si4330 offers advanced radio features including continuous frequency

coverage from 240–960 MHzThe Si4330’s high level of integration offers reduced

BOM cost while simplifying the overall system design. The extremely low receive

sensitivity (–118 dBm) ensures extended range and improved link performance.

Built-in antenna diversity and support for frequency hopping can be used to

further extend range and enhance performance.

Additional system features such as an automatic wake-up timer, low battery

detector, 64 byte RX FIFO, automatic packet handling, and preamble detection

reduce overall current consumption and allow the use of lower-cost system

MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset

(POR), and GPIOs further reduce overall system cost and size.

The Si4330’s digital receive architecture features a high-performance ADC and

DSP based modem which performs demodulation, filtering, and packet handling

for increased flexibility and performance. This digital architecture simplifies

system design while allowing for the use of lower-end MCUs.

Frequency Range = 240–960 MHz

Sensitivity = –118 dBm

Low Power Consumption

18.5 mA receive

Data Rate = 1 to 128 kbps

Power Supply = 1.8 to 3.6 V

Ultra low power shutdown mode

Digital RSSI

Wake-up timer

Auto-frequency calibration (AFC)

Clear channel assessment

Programmable RX BW 2.6–620 kHz

Programmable packet handler

Programmable GPIOs

Embedded antenna diversity

algorithm

Configurable packet structure

Preamble detector

RX 64 byte FIFO

Low battery detector

Temperature sensor and 8-bit ADC

–40 to +85 °C temperature range

Integrated voltage regulators

Frequency hopping capability

On-chip crystal tuning

20-Pin QFN package

FSK, GFSK, and OOK modulation

Low BOM

Power-on-reset (POR)

Remote control

Home security & alarm

Teleme tr y

Personal data logging

Toy control

Tire pressure monitoring

Wireless PC peripherals

Remote meter reading

Remote keyless entry

Home automation

Industrial control

Sensor networks

Health monitors

Tag readers

Patents pending

Ordering Information:

See page 139.

Pin Assignments

VDD_RF 1

6789

19 18 1720

RXp

RXn

SCLK

SDI

SDO

VDD_DIG

GPIO_0

GPIO_1

GPIO_2

XIN

XOUT

SDN

nIRQ

Metal

Paddle

511VR_IF NC

VDR nSEL

Si4330

2 Preliminary Rev 0.2

Functional Block Diagram

LPF CP

Mixers PGA

AGC Control

VCO

SPI, & Controller

Digital Logic

PFD

RFn

GPIO_2

GPIO_1 Xout

Xin

Digital Modem

Digital LDO

RC 32K OSC

30M XTAL

OSC

RF LDO

IF LDO

VCO LDO PLL LDO

BIAS

SDN

ANTDIV

Low Power

Digital LDO

POR

Temp

Sensor

VR_DIG

GPIO_0

VDD_DIG

SDO

SDI

SCLK

VDD_DIG

VR_IF

LBD

nSEL

VDD_RF

8Bit

ADC

RFp ADC

Si4330

Preliminary Rev 0.2 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.1. Definition of Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.4. Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.5. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.6. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1. FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.1. RX LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.2. RX I-Q Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.3. Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.4. ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.5. Digital Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.6. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

5.7. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

5.8. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.1. RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

6.3. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.5. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.6. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.7. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

7. RX Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

7.1. Modem Settings for FSK and GFSK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

7.2. Modem Settings for OOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

8. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

8.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

8.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

8.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

8.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Si4330

4 Preliminary Rev 0.2

8.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

8.7. Low Duty Cycle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

8.8. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

8.9. Antenna-Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8.10. RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

13. Pin Descriptions: Si4330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Si4330

Preliminary Rev 0.2 5

LIST OF FIGURES

Figure 1. RX Application Example............................................................................................ 14

Figure 2. SPI Timing..................................................................................................................16

Figure 3. SPI Timing—READ Mode ..........................................................................................17

Figure 4. SPI Timing—Burst Write Mode ..................................................................................17

Figure 5. SPI Timing—Burst Read Mode ..................................................................................17

Figure 6. State Machine Diagram..............................................................................................18

Figure 7. RX Timing ..................................................................................................................22

Figure 8. Frequency Deviation ..................................................................................................26

Figure 9. Sensitivity at 1% PER vs. Carrier Frequency Offset ..................................................27

Figure 10. PLL Synthesizer Block Diagram...............................................................................31

Figure 11. FIFO Threshold........................................................................................................33

Figure 12. Packet Structure.......................................................................................................34

Figure 13. Required RX Packet Structure with Packet Handler Disabled .................................34

Figure 14. Multiple Packets in RX Packet Handler....................................................................35

Figure 15. Multiple Packets in RX with CRC or Header Error ...................................................35

Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37

Figure 17. POR Glitch Parameters............................................................................................45

Figure 18. General Purpose ADC Architecture .........................................................................47

Figure 19. ADC Differential Input Example—Bridge Sensor .....................................................48

Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation...................49

Figure 21. Temperature Ranges using ADC8 ...........................................................................51

Figure 22. WUT Interrupt and WUT Operation..........................................................................54

Figure 23. Low Duty Cycle Mode ..............................................................................................55

Figure 24. RSSI Value vs. Input Power.....................................................................................58

Figure 25. Receiver—Schematic...............................................................................................59

Figure 26. Receiver—Top .........................................................................................................61

Figure 27. Receiver—Top Silkscreen........................................................................................61

Figure 28. Receiver—Bottom ....................................................................................................62

Figure 29. Sensitivity vs. Data Rate ..........................................................................................63

Figure 30. Receiver Selectivity..................................................................................................64

Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ...........................65

Figure 32. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 65

Figure 33. RX LNA Matching.....................................................................................................67

Figure 34. QFN-20 Package Dimensions................................................................................140

Figure 35. QFN-20 Landing Pattern Dimensions .................................................................... 140

Si4330

Preliminary Rev 0.2 6

LIST OF TABLES

Table 1. DC Characteristics .......................................................................................................7

Table 2. Synthesizer AC Electrical Characteristics1 ...................................................................8

Table 3. Receiver AC Electrical Characteristics1.......................................................................9

Table 4. Auxiliary Block Specifications1 ...................................................................................10

Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ...................................11

Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) ..............................................11

Table 7. Absolute Maximum Ratings ........................................................................................12

Table 8. Operating Modes ........................................................................................................15

Table 9. Serial Interface Timing Parameters ............................................................................16

Table 10. Operating Modes ......................................................................................................18

Table 11. Frequency Band Selection .......................................................................................24

Table 12. RX Packet Handler Configuration ............................................................................35

Table 13. Packet Handler Registers .........................................................................................36

Table 14. Minimum Receiver Settling Time ..............................................................................38

Table 15. RX Modem Configurations for FSK and GFSK ........................................................39

Table 16. Filter Bandwidth Parameters ....................................................................................41

Table 17. Channel Filter Bandwidth Settings ...........................................................................42

Table 18. ndec[2:0] Settings .....................................................................................................43

Table 19. RX Modem Configuration for OOK with Manchester Disabled .................................44

Table 20. RX Modem Configuration for OOK with Manchester Enabled .................................44

Table 21. POR Parameters ......................................................................................................45

Table 22. Temperature Sensor Range .....................................................................................50

Table 23. Antenna Diversity Control ......................................................................................... 57

Table 24. Receiver Bill of Materials ..........................................................................................60

Table 25. Recommended Crystal Parameters .........................................................................66

Table 26. RX Matching for Different Bands ..............................................................................67

Table 27. Register Descriptions ...............................................................................................68

Table 28. Interrupt or Status 1 Bit Set/Clear Description .........................................................73

Table 29. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts? .............73

Table 30. Interrupt or Status 2 Bit Set/Clear Description ........................................................75

Table 31. Detailed Description of Status Registers when not Enabled as Interrupts ...............75

Table 32. Internal Analog Signals Available on the Analog Test Bus ....................................114

Table 33. Internal Digital Signals Available on the Digital Test Bus .......................................115

Si4330

Preliminary Rev 0.2 7

1. Electrical Specifications

Table 1. DC Characteristics

Parameter Symbol Conditions Min Typ Max Units

Supply Voltage Range Vdd 1.8 3.0 3.6 V

Power Saving Modes IShutdown RC Oscillator, Main Digital Regulator,

and Low Power Digital Regulator OFF2—10TBDnA

IStandby Low Power Digital Regulator ON (Register values retained)

and Main Digital Regulator, and RC Oscillator OFF1—400— nA

ISleep RC Oscillator and Low Power Digital Regulator ON

(Register values retained) and Main Digital Regulator OFF1—800— nA

ISensor-LBD Main Digital Regulator and Low Battery Detector ON,

Crystal Oscillator and all other blocks OFF2—1—µA

ISensor-TS Main Digital Regulator and Temperature Sensor ON,

Crystal Oscillator and all other blocks OFF2—1—µA

IReady Crystal Oscillator and Main Digital Regulator ON,

all other blocks OFF. Crystal Oscillator buffer disabled1—600— µA

TUNE Mode Current ITune Synthesizer and regulators enabled — 9.5 — mA

RX Mode Current IRX —18.5— mA

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Si4330

8 Preliminary Rev 0.2

Table 2. Synthesizer AC Electrical Characteristics1

Parameter Symbol Conditions Min Typ Max Units

Synthesizer Frequency

Range

FSYNTH-LB Low Band 240 — 480 MHz

FSYNTH-HB High Band 480 — 960 MHz

Synthesizer Frequency

Resolution2

FRES-LB Low Band — 156.25 — Hz

FRES-HB High Band — 312.5 — Hz

Reference Frequency fREF fcrystal /3 — 10 — MHz

Reference Frequency

Input Level2

fREF_LV When using reference frequency instead

of crystal. Measured peak-to-peak (VPP)

0.7 — 1.6 V

Synthesizer Settling Time2tLOCK Measured from leaving Ready mode with

XOSC running to any frequency includ-

ing VCO Calibration

—200— µs

Residual FM2FRMS Integrated over 250 kHz bandwidth

(500 Hz lower bound of integration)

—2 4kHz

RMS

Phase Noise2L(fM)F = 10 kHz — –80 — dBc/Hz

F = 100 kHz — –90 — dBc/Hz

F = 1 MHz — –115 — dBc/Hz

F = 10 MHz — –130 — dBc/Hz

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Si4330

Preliminary Rev 0.2 9

Table 3. Receiver AC Electrical Characteristics1

Parameter Symbol Conditions Min Typ Max Units

RX Frequency

Range

FSYNTH-LB Low Band 240 — 480 MHz

FSYNTH-HB High Band 480 — 960 MHz

RX Sensitivity PRX_2 (BER < 0.1%)

(2 kbps, GFSK, BT = 0.5,

f = 5kHz)

—–118—dBm

PRX_40 (BER < 0.1%)

(40 kbps, GFSK, BT = 0.5,

f = 20 kHz)2

— –107 —dBm

PRX_100 (BER < 0.1%)

(100 kbps, GFSK, BT = 0.5,

f = 50 kHz)2

— –103 —dBm

PRX_125 (BER < 0.1%)

(125 kbps, GFSK, BT = 0.5,

f = 62.5 kHz)1

— –101 —dBm

PRX_OOK (BER < 0.1%)

(4.8 kbps, 350 kHz BW, OOK)2

—–110—dBm

(BER < 0.1%)

(40kbps,400kHzBW,OOK)

— –102 —dBm

RX Bandwidth2BW 2.6 — 620 kHz

Residual BER

Performance2

PRX_RES Up to +5 dBm Input Level — 0 0.1 ppm

Input Intercept Point,

3rd Order2

IIP3RX f1= 915 MHz, f2= 915 MHz,

P1= P2= –40 dBm

—–20—dBm

LNA Input Impedance2

(Unmatched, measured

differentially across RX

input pins)

RIN-RX 915 MHz — 40–55j — 

868 MHz — 44–58j —

433 MHz — 79–110j —

315 MHz — 96–134j —

RSSI Resolution RESRSSI — ±0.5 — dB

1-Ch Offset Selectivity2

(BER < 0.1%)

C/I1-CH Desired Ref Signal 3 dB above sensitivity.

Interferer and desired modulated with

40 kbps F = 20 kHz GFSK with BT = 0.5,

channel spacing = 150 kHz

—–31—dB

2-Ch Offset Selectivity2

(BER < 0.1%)

C/I2-CH —–35—dB

3-Ch Offset Selectivity2

(BER < 0.1%)

C/I3-CH —–40—dB

Blocking at 1 MHz21MBLOCK Desired Ref Signal 3 dB above sensitivity.

Interferer and desired modulated with

40 kbps F = 20 kHz GFSK with BT = 0.5

—–52—dB

Blocking at 4 MHz24MBLOCK —–56—dB

Blocking at 8 MHz28MBLOCK —–63—dB

Image Rejection2ImREJ IF=937 kHz — –30 — dB

Spurious Emissions2POB_RX1 Measured at RX pins

(LO feed through)

— — –54 dBm

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

Si4330

10 Preliminary Rev 0.2

Table 4. Auxiliary Block Specifications1

Parameter Symbol Conditions Min Typ Max Units

Temperature Sensor

Accuracy2

TSAWhen calibrated using temp

sensor offset register

—0.5—°C

Temperature Sensor

Sensitivity2

TSS—5—mV/°C

Low Battery Detector

Resolution2

LBDRES —50—mV

Low Battery Detector

Conversion Time2

LBDCT —250—µs

Microcontroller Clock

Output Frequency

MC Configurable to 30 MHz,

15 MHz, 10 MHz, 4 MHz,

3MHz,2MHz,1MHz,or

32.768 kHz

32.768K — 30M Hz

General Purpose ADC

Accuracy2

ADCENB —8—bit

General Purpose ADC

Resolution2

ADCRES —4—mV

Temp Sensor & General

Purpose ADC Conversion

Time2

ADCCT — 305 — µsec

30 MHz XTAL Start-Up time t30M —1—ms

30 MHz XTAL Cap

Resolution2

30MRES —97—fF

32 kHz XTAL Start-Up Time2t32k —6—sec

32 kHz XTAL Accuracy232KRES —100—ppm

32 kHz RC OSC Accuracy232KRCRES —2500—ppm

POR Reset Time tPOR —16—ms

Software Reset Time2tsoft —100—µs

Notes:

1. All specification guaranteed by production test unless otherwise noted.

2. Guaranteed by qualification.

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