TABLE
OF
CONTENTS
CHAPTER
4.
PRINCIPLES
OF
OPERATION
....-..eese08
4.1
INTRODUCTION.
ccccccccccccccsvececvcesccseseresseenesessese
4.2
CENTRAL
PROCESSOR
UNIT
(CPU)
ccccsecccccceccccccscccccescece
»
4-
4-
—
4-
-2.1
CPU
FUNCTIONAL
DESCRIPTION.
.ccccccccccvccccssecesseee
4-
2
TIMING
AND
CONTROL
UNIT.
ccccsccccccccesesensevcsscses
4=
03
ARITHMETIC
UNIT.
.ccccccncvcsvcccccnccssenesssceveeese
47
-4
MEMORY
MANAGEMENT.
«200.
5
OPERATING
MODES...
.ccccccaccssscnscsissosssssevcssece
A>
4.2.5.1
Absolute
Addressing.
..ccccccccceccsecccscesces
4>
4.2.5.2
Virtual
(Segmented/Paging)
Addressing........
4-
4.2.6
SEGMENT
TABLE
LOOKASIDE
BUFFER
(STLB).ccccccerececses
4-
4.2.7
CACHE
MEMORY.
..ccccccccvevce
4.2.7.1
CPU
Cache
Reads..
eeeerereeeseseeesneeeteerees
es
eneeen
4-
Oo
CO
On
SAI
OY UT
Re bP
eeeeeeeesneearesreeenereeser
4-10
eeerererescecereeesesereerenessese
4-10
»2.7.2
CPU
Cache
WriteS.....eseee.
207.3
DMX
Cache
CycleS....ccccccnccccccccvesercsees
4-1]
2267.4
Cache/STLB
Summary.
..ccccccccccccccccscscssees
4-1]
FRESH.
ccc
esececccccccncccnccccccsesveccccnsoscesece
4-1]
PROCESSOR
MANAGEMENT...
ccccescceccsccccvessscccscceces
4-]]
4.2.9.1
Process
Exchange.
..ccccccrccccccccccecsecsees
4-12
4.2.9.2
Procedure
Call.cwcccccccccvccccccccosvccceees
4-13
4.2.10
ERROR
MANAGEMENT.
.occccccccccncvccvccvccsscccccccses
4-14
Peeeeeeeaneeeneene
4-11
Bobb
&
4.2.10.1
TrapS..ccccuccccccsccvccnscscvsccssscceceses
4-14
4.2
e2
FAULtSs
wceccccvcccccvvccsccessereseccescssse
4-14
10.2.1
Restricted
InsStruction.....seceseesseee
4-15
-10.2.2
Unimplemented
Instruction...ceceeseeeee
4-15
10.2.3
Tllegal
Instruction...
.ccccccecsecsescee
4-15
CHECKS.
ec
cecccccccccrccscvccsescessceceseces
4-15
el
Machine CheckS...cceccccccscccccsecseee
47-16
02
Power
Fallescccccccccccccsccecesscecees
4-16
03
Memory
Parity.
..cccccccccscccsccceseses
4-16
o4
I/O
Parityreccvcccvescescecsccvcesesese
4°18
CLLUPES
.
occ
nccccsvecccscccccsvccsassvcces
4-19
Device
Driver
PYOGramS...secccecseccees
4-19
PYOGraM
VECCOLINd.
.coccescccccsccceeses
4-20
Interrupt
ModeS..wsscccccccccccccsvesees
4-2]
Interrupts
in
Process
Exchange
Mode....
4-22
Memory
Increment
InterruptS....cecscesee
4-22
Interrupt
Inhibits/Enables...secscesese
4°23
Override
Inhibits...
.ccccccccecccecveece
4-23
Interrupt
Priority
Network....sssccesees
4-23
Highest
Priority
Active
Interrupt......
4-24
RAL
I/O
MANAGEMENT...
cccccccscccccvccccseccccs
4-24
Programmed
I/O
(PIO)
.occcccccccccvcccccescee
4-26
1.1.1
Output/Input
The
A
Register
(OTA/INA)..
4-27
1.1.2
Skip
On
Condition
Set
(SKS)
.scessecseee
4-27
1. 1.
3
Output
Control
Pulse
(OCP)..ecececevces
4-28
rect
Memory
Transfer
(DMX)
...cccesceccreee
4-28
1
Direct
Memory
AccesSS
(DMA)..ccccecesees
4-29
Direct
Memory
Transfers
(DMT)
..cceccsess
4°32
Direct
Memory
Channel
(DMC)...scccesees
4734
Direct
Memory
Queue
(DMO)...csceescecees
4-36
Burst
Mode
DMA
(BDMA).cecccccccscccsens
4738
1
1
4.2.10.3
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