Oki ML60852A Instructions d'utilisation
ML60852A
Application Manual
USB device controller
Version 1.02
FEAL60852A-02
DATE: OCT. 9, 2001 1
ML60852A Application Manual
1. INTRODUCTION--------------------------------------------------------------1
2. EXAMPLES OF USB TRANSFER PROCEDURE---------------------6
3. EXTERNAL INTERFACE------------------------------------------------- 19
4. INTERRUPTS----------------------------------------------------------------- 29
5. OTHER FUNCTIONS------------------------------------------------------- 33
6. HANDLING UNUSED PINS----------------------------------------------- 35
7. DIFFERENCES IN PIN ASSIGNMENT BETWEEN
ML60851 AND ML60852A ------------------------------------------------- 37
CONTENTS
1. INTRODUCTION ...........................................................................................................................1
1.1. Product Features...............................................................................................................................1
1.2. Pin Configuration and Description...................................................................................................2
1.2.1. Pin configuration..............................................................................................................................2
1.2.2. Pin description..................................................................................................................................3
1.3. Example of External Connections....................................................................................................4
1.3.1. Example of connections between MSM66573 (OKI make) and ML60852A .................................4
1.3.2 Example of connections between H8/3048 (Hitachi make) and ML60852A ..................................5
2. EXAMPLES OF USB TRANSFER PROCEDURE........................................................................6
2.1. Device Initialization.........................................................................................................................6
2.1.1. Setting the operating conditions of ML60852A...............................................................................6
2.1.2. Settings based on standard request...................................................................................................6
2.2. Control Transfer...............................................................................................................................7
2.2.1. Control transfer ................................................................................................................................7
2.2.2. Setup ready interrupt procedure.......................................................................................................8
2.2.3. Reading received data in receive packet ready interrupt procedure.................................................9
2.2.4. Writing transmit data in transmit packet ready interrupt procedure...............................................10
2.3. Bulk Transfer..................................................................................................................................11
2.3.1. Outline of bulk transfer..................................................................................................................11
2.3.2. Packet ready interrupt procedure in Bulk-Out Transfer.................................................................12
2.3.3. Packet ready interrupt procedure in Bulk-In Transfer....................................................................13
2.4. Interrupt Transfer ...........................................................................................................................14
2.4.1. Outline of interrupt transfer............................................................................................................14
2.5. Isochronous Transfer......................................................................................................................15
2.5.1. Outline of isochronous transfer......................................................................................................15
2.5.2. Outline flow of isochronous-out transfer .......................................................................................16
2.5.3. Outline flow of isochronous-in transfer.........................................................................................17
2.5.4. Errors in isochronous-out transfer..................................................................................................18
3. EXTERNAL INTERFACE............................................................................................................19
3.1. Bus Interface ..................................................................................................................................19
3.1.1. ADSEL pin.....................................................................................................................................19
3.1.2. ALE/PUCTL pin............................................................................................................................19
3.2. DMA Interface ...............................................................................................................................20
3.2.1. Selection of –DREQ and DACK polarities....................................................................................20
3.2.2. –DREQ Active conditions..............................................................................................................20
3.2.2.1. During transmission.......................................................................................................................20
3.2.2.2. During reception ............................................................................................................................20
3.2.3. DMA Enable..................................................................................................................................20
3.2.4. Selecting the EP that uses DMA transfer.......................................................................................20
3.2.5. Address modes during DMA transfer ............................................................................................21
3.2.6. Transfer modes during DMA transfer............................................................................................21
3.2.7. Byte count data insertion................................................................................................................21
3.2.8. Transfer data width during DMA transfer......................................................................................21
3.2.9. Interrupting DMA transfer.............................................................................................................21
3.2.10. –DREQ Signal interval during single transfer ...............................................................................22
3.2.11. Setting packet ready during DMA transfer ....................................................................................22
3.3. Interrupt Interface...........................................................................................................................23
3.3.1. Selection of –INTR pin polarity.....................................................................................................23
3.3.2. Processing method for nested interrupts ........................................................................................23
3.4. Oscillation Circuit..........................................................................................................................24
3.4.1. Oscillation frequency.....................................................................................................................24
3.4.2. Oscillator circuit configuration examples ......................................................................................24
3.4.2.1. Using a ceramic resonator..............................................................................................................25
3.4.3. Supplying an external clock...........................................................................................................26
3.4.4. Stopping the oscillator circuit ........................................................................................................26
3.5. USB Interface.................................................................................................................................27
3.5.1. Series resistors in the D+/D– lines.................................................................................................27
3.5.2. VBUS monitoring ..........................................................................................................................28
4. INTERRUPTS ...............................................................................................................................29
4.1. Setup Ready ...................................................................................................................................30
4.2. Receive Packet Ready....................................................................................................................30
4.3. Transmit Packet Ready...................................................................................................................31
4.4. SOF ................................................................................................................................................31
4.5. USB Bus Reset Assert....................................................................................................................32
4.6. USB Bus Reset Deassert................................................................................................................32
4.7. Suspend State...............................................................................................................................322
4.8. Awake...........................................................................................................................................322
5. OTHER FUNCTIONS...................................................................................................................33
5.1. 5EP Mode and 6EP Mode..............................................................................................................33
5.2. System Reset..................................................................................................................................33
5.3. Self-powered and Bus-powered.....................................................................................................33
5.4. Suspend Function...........................................................................................................................33
5.5. Remote Wakeup.............................................................................................................................34
6. HANDLING UNUSED PINS........................................................................................................35
6.1. Bus Access Control Pins-1 (A6 to A0) ..........................................................................................35
6.2. Bus Access Control Pin-2 (ALE/PUCTL).....................................................................................35
6.3. DMA Transfer Control Pins (D15 to D8, –DREQ0, –DREQ1, DACK0, DACK1) ......................35
6.4. Crystal Connection Pin (XOUT)....................................................................................................35
6.5. Test Pins (TEST1, TEST2).............................................................................................................36
7. DIFFERENCEES IN PIN ASSIGNMENT BETWEEN ML60851 AND ML60852A.................37
7.1. Test Pin ⇔GND (pin 5, pin 17) ....................................................................................................37
7.2. VCC5 ⇒DACK1 Pin (pin 18)......................................................................................................38
7.3. ALE Pin ⇒ALE/PUCTL Pin (pin 23) ..........................................................................................38
7.4. A7 Pin ⇒–DREQ1 Pin (pin 25)....................................................................................................38
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1. INTRODUCTION
The ML60852A is a general-purpose device controller conforming to the Universal Serial Bus (USB)
Standard Rev.1.1. This LSI contains a USB serial interface engine, a USB transceiver, FIFOs, control
and status registers, application interface circuits, and an oscillator circuit, and allows easy realization of
a USB system.
This LSI supports control transfer, bulk transfer, interrupt transfer, and isochronous transfer as the data
transfer modes and allows five or six end points to be used.
1.1. Product Features
• Conforms to USB1.1.
• Supports Full-speed (12 Mbps).
• Supports four data transfer types:
Control transfer, bulk transfer, interrupt transfer, and isochronous transfer.
• Five or six end points
• Built-in FIFO for data storage
• The FIFO for EP1, EP2, EP4, and EP5 has a 2-layer configuration.
• 8 or 16 bit DMA Transfer is possible (EP1, EP2, EP4, EP5) with two channels.
• Supports bus-powered devices
With the operation mode setting, the ML60852A detects the suspend condition automatically and
enters the low-power mode. The LSI automatically returns to the normal operation when it detects the
resume condition.
• Built-in USB transceiver circuit
•V
CC = 3.0 to 3.6 V
• Can be interfaced with 5 V circuits (5 V tolerant input, TTL output).
• Built-in 6 MHz/12 MHz selectable oscillator circuit
• Packages : 44-pin QFP/TQFP
56-pin LGA
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1.2. Pin Configuration and Description
1.2.1. Pin configuration
44-Pin QFP (Top View)
56-Pin LGA (Transparent View)
33
32
31
30
29
28
27
26
25
24
23
DACK0
A0
A1
A2
A3
A4
A5
A6
–DREQ1
ADSEL
A
LE/PUCTL
D+
D–
VCC
TEST1
GND
XIN
XOUT
–CS
–RD
–WR
–RESET
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
AD0
AD1
AD2
AD3
VCC
GND
AD4
AD5
AD6
AD7
–DREQ0
–INTR
D15
D14
D13
D12
TEST2
DACK1
D11
D10
D9
D8
J
H
G
F
E
D
C
B
A
NC D8 D9 D11 TEST2 D12 D14 –INTR NC
ALE/
PUCTL NC D10 DACK1 NC D13 D15 NC –RESET
–DREQ1 ADSEL –RD –WR
A5 A6 –XOUT –CS
A4 NC NC –XIN
A2 A3 TEST1 GND
A0 A1 D– VCC
DACK1 NC AD7 AD5 NC DACK1 AD2 NC D+
NC –DREQ0 AD6 AD4 GND AD3 AD1 AD0 NC
9 8 7 6 5 4 3 2 1
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1.2.2. Pin description
USB Interface
Signal name I/O Polarity Description
D+ I/O — Pin for connecting USB Data (+)
D– I/O — Pin for connecting USB Data (–)
When D+ and D– are indeterminate, it is impossible to write data in the registers that are reset by a USB
bus reset.
Crystal oscillator interface
Signal name I/O Polarity Description
XIN I — Pin for connecting a crystal
XOUT O — Pin for connecting a crystal
Application interface
Signal name I/O Polarity Description
D15 to D8 I/O — Upper byte of data bus (MSB)
AD7 to AD0 I/O — Lower byte of the data bus (LSB) and address
input pin
A6 to A0 I — Address input pins
–CS I Negative logic Chip select signal input pin
–RD I Negative logic Read signal input pin
–WR I Negative logic Write signal input pin
–INTR O (*1) Interrupt request signal output pin
–DREQ0/–DREQ1 O (*1) DMA Request signal output pins
DACK0/DACK1 I (*2) DMA Acknowledge signal input pins
ALE/PUCTL I (*3) Address latch enable signal input and pull-up
resistor control pin
ADSEL I Address input format signal input pin
–RESET I Negative logic Reset signal input pin
*1: Although the default value immediately after reset is negative logic, the polarity can be changed by
overwriting the polarity selection register.
*2: Although the default value immediately after reset is positive logic, the polarity can be changed by
overwriting the polarity selection register.
*3: The polarity becomes positive logic when this signal functions as an address latch enable (ALE)
signal.
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1.3. Example of External Connections
1.3.1. Example of connections between MSM66573 (OKI make) and ML60852A
Notes:
*1: 5 to 3.3 V
*2: Address decode
*3: Pull-up control is used in this connection.
*4: This circuit is bus-powered.
Figure 1 Example of connections between OKI’s 16-bit microcontroller
MSM66573 and ML60852A
VDD
P127
D7 to D0
A6 to A0
A15 to A8
–RD
–WR
EXTINT1
VSS
MSM66573
ALE/PUCTL
VCC
AD7 to AD0 D+
D–
A6 to A0 XIN
–CS XOUT
–RD DACK0/DACK1
–WR D15-D8
–INTR ADSEL
RESET TEST1/TEST2
GND
ML60852A
8
7
12 MHz
5 V
*2
USB
Connector
VBUS
D+
D–
GND
100 kΩ
1.5 kΩ
22 Ω
100 kΩ
8
220 kΩ
*1
3.3 V
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1.3.2. Example of connections between H8/3048 (Hitachi make) and ML60852A
Notes:
*1: 5 to 3.3 V
*2: Pull-up control is used in this connection.
*3: This circuit is bus-powered.
Figure 2 Example of connections between Hitachi’s 16-bit microcontroller
(DMA transfer in dual address mode) H8/3048 and ML60852A
VDD
D15 to D8
D7 to D0
A7 to A1
–CS0
–CS1
–RD
–HWR
–IRQ1
–RESO
–DREQ0
VSS
H8/3048
ALE/PUCTL
VCC
D+
AD7 to AD0 D–
XIN
D15 to D8 XOUT
A6 to A0
–CS DACK0/DACK1
–RD ADSEL
–WR TEST1/TEST2
–INTR VSS
–RESET
–DREQ0
ML60852
A
8
8
USB
Connecto
r
VBUS
D+
D–
GND
100 kΩ
100 kΩ
*1
3.3 V
1.5 kΩ
22 Ω
220 kΩ
7
12 MHz
5 V
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2. EXAMPLES OF USB TRANSFER PROCEDURE
This chapter gives a description of a sample procedure for carrying out USB communication using the
ML60852A.
2.1. Device Initialization
The device initialization consists of setting the hardware operating conditions and settings based on the
standard request from a host computer.
2.1.1. Setting the operating conditions of ML60852A
Carry out the settings of the operating conditions of the ML60852A to suit the system after referring to
Chapter 3 “EXTERNAL INTERFACE”.
2.1.2. Settings based on standard request
Eleven types of standard requests have been defined in USB Standard Rev. 1.1 (See Chapter 9 of the
USB Standard Rev. 1.1 for detailed definitions of the standard requests). Standard requests are issued
from a host computer via a control pipe. Some of these requests require device settings to be changed.
Hence, it is necessary for the USB firmware to support these requests and set device registers
accordingly.
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