Numark D2 Director Manuel utilisateur
MODEL: D
2
DIRECTOR
SPECIFICATION
STANDARD
OUTPUT LEVEL………………………………….1.0±0.2Vms(1KHZ 0dB)
S/N RATIO…………………………………………MORE THAN 90dB
FREQUENCY RESPONSE……………………...20Hz~20KHz
2dB
DYNAMIC RANGE………………………………..MORE THAN 90dB
CHAMMEL SEPARATION……………………….MORE THAN 90dB
CHANNEL BALANCE………………...................
1dB
HARMONIC DISTORTION……………………….LESS THAN 0.01%
SERVICE MANUAL
NH00 Top Level System Description
rev 0
PG 15 Jan 07
Introduction
The NH00 is a rack mount DJ audio player, playin content from USB devices such as flash drives
and hard discs. Effects are available that are useful to a DJ: pitch shiftin , scratchin , loopin and
beatkeepin . A lar e LCD display is featured alon with an innovative user interface. The
electronics are implemented in 3 PCBs; the CPU board, the I/O board and the Control board.
This document describes the top level desi n of the system, and should be read in conjunction with
the circuit descriptions of the individual boards.
Block Diagram
Microcontroller
LEDs
Switches
Scratch Wheels
Pitch faders
PSU & control
CODEC
CPU BOARD LCD MODULE Audio out
4 channels Power in
+12V DC
I2S Audio
SPI
I/O BOARD
CONTROL BOARD
USB1 USB2 USB3
CPU Board
This is the main di ital 'en ine' of the product featurin an ARM CPU runnin the system software
and a DSP providin some additional audio processin . The CPU board has the followin main
interfaces:
•3 x USB host ports. One connects to the port on the front of the unit and two connect to the
rear panel.
•LCD display interface. This connects to the LCD via the I/O board.
•I2S audio connects to the audio codec on the I/O board.
•SPI bus for communication between the system CPU and the control board microcontroller.
I O Board
The I/O board provides the power supply and power control for the system, and the audio codec and
audio output circuitry. It also acts as 'backplane', routin si nals between the CPU board and the
control board and LCD module.
Control Board
This board provides a control panel with switches, LEDs, scratch wheels and pitch faders. A
microcontroller interfaces to these controls and communicates with the system CPU via an SPI bus.
LCD Module
A Winstar 320 x 240 LCD module is used for the user interface display.
AKAI 9307 CPU Board Circuit Description
rev 0
PG 11 Jan 07
Introduction
The 9307 CPU board is used in the NH00 and KA3. It is the ain digital 'engine' providing the
ain syste CPU and DSP for audio processing. This docu ent provides a circuit description for
this board.
Block Diagram
ARM CPU
EP9307
SHARC DSP
ADSP-21261
SDRAM
256MBit
RTC
32kHz
FLASH
64MBit
To control
board
x3
x2
x3
x2
I2S audio I2S audio
USB x3
Serial x2
SPI bus
To codec
SH T 1 – CPU
This sheet shows the syste CPU and associated circuitry. IC4 is a Cirrus EP9307 ARM CPU. The
IC runs fro a 1.8V core supply (VCCCORE) and a 3.3V I/O supply (VCCIO).
IC2 is a 64Mbit flash e ory for progra and data storage. IC1 and IC3 are SDRAM e ory,
these run at 100MHz clock speed.
IC6 is a reset generator that onitors both the core and I/O supply rails and keeps the CPU in reset
until both supplies are stable.
IC14 is a 14.7456MHz oscillator odule. This clock is used by the CPU IC which features several
internal phase locked loops to generate the various clocks required; the 100MHz SDRAM clock for
exa ple.
IC5 is a real ti e clock (RTC) IC that provides a 32kHz clock used by the ARM CPU. Note that we
do not currently ake use of the RTC function, it is there only to provide the 32kHz clock for the
CPU. This is an i portant clock and the CPU will not boot without it.
Provision has been ade to use a back up battery for the RTC. Were this to be used, it would
connect to PL10 to provide power for the RTC only when the ain power supply is switched off.
The resistors in the lower left corner of this sheet (R31, R33-34, R36, R39, R41, R43-44), are
i portant configuration resistors, these ensure that the CPU boots in the correct ode.
GPIOs and interrupts
Signals GPIO0-14 are general purpose I/O signals that are used to control a variety of functions as
described in the table below.
GPIO Input/Output Function
GPIO0
GPIO1
GPIO2 Input USB power fault. 1=Nor al. 0=USB power fault
GPIO3 Output USB power enable. 0=power enabled. 1=Disabled
GPIO4 Input !OFF power down request signal fro I/O board.
Nor ally high. Low to request power down.
GPIO5 Input POWER. State of front panel power switch. High when
button is pressed
GPIO6 Output !DAC_RESET. Nor ally high. Low to reset audio DAC
GPIO7 Output !ADC_RESET. Nor ally high. Low to reset audio ADC
GPIO8 Input FSTART_A. Fader start. Used in KA3 but not NH00.
GPIO9 Input FSTART_B. Fader start. Used in KA3 but not NH00.
GPIO10 Input JUKEBOX_MODE. Used in KA3 but not NH00.
GPIO11 Output Controls USB switch IC8 for iPod interface. 1=iPod in
USB ode. 0= iPod in serial ode. (Not used in NH00)
GPIO12 Not used
GPIO13 Output DSP SPIDS. Nor ally high. Low when progra ing
software into DSP.
GPIO14 Output !DSP_RESET. Nor ally high. Low to reset Sharc DSP
INT0 Interrupt input POWERFAIL. Nor ally low. High to indicate power
failure (i.e power has been re oved)
SPI Bus
The SPI bus connects the ARM CPU to the Sharc DSP and the PIC icrocontroller on the Control
board. The SPI bus is used at power up to load software into the Sharc DSP. For this, the ARM
CPU is the SPI aster and the Sharc DSP is the SPI slave. Once this is co pleted the SPI bus is
then used for co unication between the control board icrocontroller and the ARM CPU. For
this, the control board icro is the SPI aster and the ARM CPU beco es a slave.
Note that a control signal TXD2 is used to tell the control board icro when it is allowed to take
over the SPI bus. TDX2 is and output fro the ARM CPU. It is high while the DSP software is
being loaded, and goes low when this is finished to indicate that the control board can beco e the
SPI aster and start co unication.
SPI bus signals
Signal Name Function Source
SSCLK SPI clock Driven by ARM while loading DSP software.
Driven by Control board icro after that.
SSFRM SPI fra e (fra es each byte) Note used when loading DSP software. Driven
by control board icro after that.
SSTX SPI data trans it Driven by ARM while loading DSP software.
Driven by Control board icro after that.
SSRX SPI data receive Driven by SHARC while loading DSP software.
Driven by ARM board icro after that.
GPIO14 SPIDS for Sharc DSP (low
while loading DSP S/W)
Driven by ARM
I2S audio signals
I2S audio interfaces are provided between the ARM CPU and the DSP. Audio can be sent in both
directions, though in the NH00 only the outputs fro the ARM are used. The DSP is the I2S aster
and the ARM is a slave. All audio on this interface is trans itted at a sa ple rate of 176.4kHz.
Signal Name Function Source
ARM-BCLK I2S bit clock (11.2896MHz) DSP
ARM-MCLK I2S aster clock (not used because ARM does
not need aster clock)
DSP
ARM-LRCLK I2S word clock (176.4kHz) DSP
ARM-SIN0 I2S data in channel 0 (not used in NH00) DSP
ARM-SIN1 I2S data in channel 1 (not used in NH00) DSP
ARM-SOUT0 I2S data out channel 0 (deck A) ARM
ARM-SOUT1 I2S data out channel 1 (deck B) ARM
ARM-SOUT2 I2S data out channel 2 (not used in NH00) ARM
USB
The ARM CPU provides 3 full speed (12Mbit/s) USB host ports. Each port uses a differential pair
of signals; USBP0/USBM0, USBP1/USBM1 and USBP2/USBM2 are the 3 ports.
I2C
An I2C port is provided; SDA (data) and SCL (clock). The ARM is the I2C aster.
This is used to configure the audio codec. It is also connected to the RTC chip although at present
the RTC chip is never co unicated with.
Serial ports
The ARM CPU provides 3 serial ports, of which we ake use of 2. TXD0/RXD0 are used for
debugging purposes, and this serial port is accessible on the NH00 I/O board. TXD1/RXD1 are not
used on the NH00 (on KA3 it is used for the iPod interface). RXD2/TXD2 are not used as a serial
port; TXD2 is a si ple control signal as entioned earlier.
Display interface
The ARM CPU drives the LCD odule using the following signals:
Signal name Function
SPCLK Pixel clock
VSYNC Vertical sync signal
HSYNC Horizontal sync signal
BLANK Blanking signal
BRIGHT Pulse width odulated (PWM) signal controls brightness of LCM backlight
P17 Used for fra e reverse signal
P12/P8/P4/P0 Used for D0..D3 4 bit video data
Status L Ds
D1 (red) and D2 (green) are status LEDs that can be used to see if the CPU has booted correctly.
Nor ally, the red LED will light briefly at power up then the green one will co e on instead.
If this fails to happen it indicates that the CPU has failed to boot for so e reason.
SH T 2 – I/O & PSU
This sheet shows the I/O connections, power supplies and power control.
Connections to I/O board
PL2-3 are 50 way high density connectors that connect the various signals to the I/O board:
I2S audio signals
I2C bus
SPI bus
LCD interface
Serial ports
Power control signals (OFF, POWER, POWERFAIL)
Codec reset signals (ADC_RESET, DAC_RESET)
USB ports
The 3 USB ports are provided on PL4-6. USB host ports are required to provide a 5V power supply.
IC9 is a protection device that is designed to protect the syste fro faults in the external USB
devices. It li its the current to a axi u of 0.9A per port, and detects short circuits. If a fault
occurs, !USBFAULT will go low. This is buffered by IC7 and reported back to the CPU. The
power for the USB ports can be turned off by the CPU using GPIO13.
IC8 is an analogue switch that switches the USB signals for one of the ports. In the KA3, PL6 is
connected to the iPod dock, and the analogue ux can disable the USB port when the iPod is used
in serial ode. In NH00, PL6 is a nor al USB port, so IC8 will always pass the USB signals.
PL9 is for the iPod serial port which is not used in NH00.
LCD backlight control
IC10 and associated co ponents provide an adjustable voltage to drive the LCM backlight. The
signal BRIGHT is a PWM signal fro the ARM CPU. R67/R69/C15 scales and filters this to a DC
level, which connects to the adjust pin of the voltage regulator IC10. IC10 will act so as to aintain
1.25V between its output and adjust pin, therefore the output will follow 1.25V above the adjust
pin. This drives the LCM backlight.
Core supply and power sequencing
IC11 is an adjustable voltage regulator providing the 1.8V core supply for the ARM CPU.
The ARM CPU needs the I/O supply to co e up so e ti e before the core supply. If this is not
done, the CPU so eti es fails to boot up due to a bug in the IC. To achieve this, a power
sequencing circuit is e ployed to turn off the input to IC11 for a short ti e at power up.
IC16 is a reset generator IC, the output of which will stay low for approxi ately 240 s after the
3.3V rail co es up. This signal is inverted by TR1 and then controls the gate of MOSFET TR2.
TR2 will therefore be off for 240 s after power up, so the 1.8V core supply will co e up 240 s
after the 3.3V rail.
SH T 3 – DSP
This sheet shows the SHARC DSP IC13, which is used for so e of the audio processing. Audio
fro the ARM is processed before being trans itted to the codec. Audio fro the codec is
processed before being trans itted to the ARM (the latter is not used in the NH00).
The DSP uses a 1.2V core provided by regulator IC18. The I/O supply is 3.3V. IC15 is a
22.5792MHz oscillator used by the DSP to generate all the clocks in needs internally using phase
locked loops.
The software for the DSP is loaded shortly after power up using the SPI bus, as described earlier.
Configuration resistors R84, R82 and R85 are i portant and ensure the DSP boot in the correct
ode with the correct internal clock frequency.
Audio interfaces
The DSP has audio interfaces to the ARM and the codec. In both cases the DSP is the I2S aster.
The interface with the ARM is descibed earlier.
The following signals ake up the interface with the codec, these run at 44.1kHz sa ple rate.
Signal Name Function Source
DSP-BCLK I2S bit clock (2.8224MHz) DSP
DSP-MCLK I2S aster clock (11.2896MHz) DSP
DSP-LRCLK I2S word clock (44.1kHz) DSP
DSP-SIN0 I2S data in channel 0 (not used in NH00) CODEC
DSP-SIN1 I2S data in channel 1 (not used in NH00) CODEC
DSP-SOUT0 I2S data out channel 0 (deck A) DSP
DSP-SOUT1 I2S data out channel 1 (deck B) DSP
DSP-SOUT2 I2S data out channel 2 (not used in NH00) DSP
Status L D
D5 is a red LED that shows the status of the DSP. Nor ally, this will turn on at power up, then turn
off while the software is loaded into the DSP, before turning on again once the software starts
running. If the behaviour is different then it indicates a proble with the DSP.
NH00 I/O Board Circuit Description
rev 0
PG 12 Jan 07
Introduction
This board is used in the NH00 DJ audio player. It includes the audio codec power supply and
power control circuit.
Block Diagram
Audio CODEC
Audio input 2 ch
(not used) Audio output 4 ch
Power supply
Power control circuit
12V Power in
System power
supplies
POWER switch To CPU board
I2S Audio to CPU
board
SHEET 1 – CODEC
This sheet shows the audio codec audio input and output circuitry muting and power supplies for
the analogue section.
The design features analogue inputs for a record function though the parts for this are not fitted
since the feature was removed from the product. 2 channels of audio are input on J3. Op-amp U3
and associated components form an input buffer having a gain of -0.4 and DC offset of +2V to
ensure the signal is at the correct levels for the codec. D3 and D8 provide limiting to ensure the
codec is not damaged in the event of large signal levels being applied. None of the components in
this section are fitted except C38 and C60; these have 0 ohm resistors fitted to ground the analogue
inputs of the codec.
U2 is a Cirrus Logic CS42406 audio codec. I2S audio is received from the CPU board for
conversion to analogue audio. I2S_TX0 and I2S_TX1 are the serial audio data for deck A and B
respectively. I2S_BCLK is the bit clock I2S_LRCLK is the word clock and I2S_MCLK is the
master clock.
The codec is configured by software via the I2C signals SDA (data) and SCL (clock).
!DAC_RESET is used to reset the DAC (active low) and !ADC_RESET resets the ADC (also
active low).
4 analogue outputs from the codec are used for Deck A (left + right) and Deck B (left + right)
outputs. These are AC coupled by C29 C50 C54 and C26 to remove the 2V DC offset that the
signal has at the codec output.
U1-A and associated components form a 2nd order low pass butterworth filter with corner frequency
of 50kHz approximately and a gain of -1.25. All 4 output channels use the same circuit.
Q1-4 are muting transistors. When switched on these clamp the audio outputs to ground to ensure
no pops or clicks are heard at the output when the system is powered up or down.
The muting is controlled by the MUTEC1 output of the codec. When MUTEC1 is high the outputs
will be muted. Transitors Q5-6 buffer the muting signal. R23 pulls the base resistors of Q1-4 down
to -4V to ensure the transistors are completely off when the system is not muted.
The MUTEC1 pin can be controlled by software to ensure that the system is muted when necessary.
MUTEC will always be high following power up and the software waits until the codec has been
initialised before taking it low. This mutes pops and thumps during power up and initialisation. The
software also controls muting at power down whether it is the user putting the unit into standby
mode or the power is unplugged. In the latter case the software receives a power fail signal to warn
it that the power is about to go away and it mutes the system before any unpleasant noises are
heard.
The audio op-amps use +/-4V supply rails. The codec +VA supply also uses the +4V rail. U9 is a
low drop out voltage regulator that derives the +4V rail from the system +5V rail. U7 is a charge
pump voltage inverter that generates a -4V supply from the +4V rail.
Autres manuels pour D2 Director
1
Ce manuel convient aux modèles suivants
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