Nepes NM500 Manuel utilisateur

NM500

User’s Manual

NeuroMem chip, 576 neurons

Version 1.6.3

Revised 04/18/2019

NM500 Manual 2

NM500 is a product manufactured exclusively by nepes (www.nepes.kr).

NM500 is subject to a license from General Vision for the NeuroMem® technology.

For information about the NeuroMem® digital neuromorphic technology, refer to the General Vision web site at

www.general-vision,com and in particular the NeuroMem Technology Reference Guide.

NM500 Manual 3

CONTENTS

1Overview................................................................................................................................................................4

1.1 Architecture .................................................................................................................................................4

1.2 The basic neuron entity................................................................................................................................5

2The control registers..............................................................................................................................................6

2.1 Neuron registers in detail.............................................................................................................................7

2.2 Registers Access Latency............................................................................................................................11

2.3 Typical latencies per operation ..................................................................................................................12

3NeuroMem bus and control lines........................................................................................................................13

3.1 Clocks, power-up and reset........................................................................................................................14

3.1.1 G_Reset, global reset .............................................................................................................................14

3.1.2 G_CLK, system clock ..............................................................................................................................14

3.1.3 CS_, power saving control line...............................................................................................................14

3.1.4 DCI..........................................................................................................................................................14

3.1.5 DCO ........................................................................................................................................................14

3.2 NeuroMem bus ..........................................................................................................................................15

3.2.1 DS...........................................................................................................................................................15

3.2.2 RW_ .......................................................................................................................................................15

3.2.3 REG[3:0] .................................................................................................................................................15

3.2.4 DATA[15:0].............................................................................................................................................16

3.2.5 RDY.........................................................................................................................................................16

3.2.6 ID_..........................................................................................................................................................16

3.2.7 UNC_ ......................................................................................................................................................16

4Typical Timings Constraints .................................................................................................................................17

4.1 Timings .......................................................................................................................................................17

4.2 Learn a vector.............................................................................................................................................18

4.3 Recognize a vector .....................................................................................................................................19

5Interconnecting chips ..........................................................................................................................................20

5.1 Counting the neurons in a chain of unknown length.................................................................................20

5.2 Verifying the proper interconnectivity of the entire chain ........................................................................20

5.3 If a chain has more than 65535 neurons....................................................................................................21

5.4 Single or multiple chains of neurons..........................................................................................................21

6Pinout ..................................................................................................................................................................22

7Mechanical specifications....................................................................................................................................25

8Electrical Specifications .......................................................................................................................................26

8.1 Recommended Operating Conditions........................................................................................................26

8.2 DC Electrical Charateristics.........................................................................................................................26

9Power Consumption ............................................................................................................................................27

9.1 Peak Power.................................................................................................................................................27

9.2 Intrinsic Power ...........................................................................................................................................27

9.3 UPower saving tips ......................................................................................................................................27

10 FAQ ......................................................................................................................................................................28

10.1 Hardware questions ...................................................................................................................................28

10.2 Functional questions ..................................................................................................................................28

10.3 What is the difference between CM1K and NM500 ..................................................................................29

NM500 Manual 4

1OVERVIEW

The NM500 chip is a fully parallel silicon neural network: it is a chain of identical elements (i.e. neurons) addressed

in parallel and which have their own “genetic” material to learn and recall patterns without running a single line of

code and without reporting to any supervising unit. In addition, the neurons fully collaborate with each other

through a bi-directional and parallel neuron bus which is the key to accuracy, adaptivity and speed performance.

Indeed, each neuron incorporates information from all the other neurons into its own learning logic and into its

response logic.

The neurons can learn and recognize input vectors autonomously and in parallel. If several neurons recognize a

pattern (i.e. “fire”), their responses can be retrieved automatically in increasing order of distance (equivalent to a

decreasing order of confidence). The information which can be read from a firing neuron includes its distance,

category, and neuron identifier. If the response of several or all firing neurons is polled, this data can be

consolidated to make a more sophisticated decision weighing the cost of uncertainty or else.

1.1 ARCHITECTURE

The NM500 chip has a unique homogeneous architecture:

-Chain of identical neurons, daisy-chained Intra-Chip and Inter-Chip

-Neuron Interconnect module (switches, no controller or supervisor) which synchronize communication

between the neurons Intra-Chip and Inter-Chip.

-All neurons have the same behavior and execute the instructions in parallel independent from the cluster

or even chip they belong to.

-Selection of one out of two classifiers: K-Nearest Neighbor (KNN) or Radial Basis Function (RBF) and more

precisely a Restricted Coulomb Energy (RCE) neural network

-Recognition time is independent of the number of neurons in use

-Automatic model generator built into the neurons

-Save and Restore of the contents of the neurons

-Simple Register Transfer Level instruction set through of 15 registers

NM500 Manual 5

1.2 THE BASIC NEURON ENTITY

The neuron cell is composed of a memory, a set of 6 registers and some logic gates. For details, please refer to

chapter 3 of the NeuroMem technology Reference Guide.

- Context register: input describing the type of pattern stored in the neuron

- Memory holds a model or prototype

- Category register: input written during a learning operation (whether supervised or unsupervised)

- Distance: output given the distance between an input pattern and the pattern stored in the Memory of

the neuron

- AIF: Active Influence Field auto-adjusted by the neuron

- MINIF: Minimum influence field of the neuron

- Identifier: Position of the neuron in the chain of neurons available

A neuron is said committed when it stores a pattern to its memory along with a category with a value different

from 0. Such action takes place when a learning operation is executed and none of the presently committed

neurons recognize the pattern with a category equal to the category to learn.

NM500 Manual 6

2THE CONTROL REGISTERS

The entire neural network whether composed of one or multiple chips can be used under 2 different modes:

Normal mode

The neurons can learn and recognize patterns. In recognition, the neurons can behave as a K-Nearest Neighbor

(KNN) or Radial Basis Function (RBF) and more precisely a Restricted Coulomb Energy (RCE) neural network.

Save-and-Restore (SR) mode

The neurons become dummy memories which can be read or written. Their automatic model generator and

search-and-sort logic are disabled. The contents of the committed neurons is a representation of the knowledge

they have built autonomously by learning examples. The SR mode allows to view, save and restore this knowledge.

NeuroMem Registers and Read/Write access under the Normal and SR mode.

Abbreviation

Description

Addr 8-bit

Normal mode

SR mode

16-bit default

NSR

Network Status Register

0x0D

0x0000

GCR

Global Control Register

0x0B

0x0001

MINIF

Minimum Influence Field

0x06

0x0002

MAXIF

Maximum Influence Field

0x07

0x4000

NCR

Neuron Context Register

0x00

0x0001

COMP

Component

0x01

0x0000

LCOMP

Last Component

0x02

0x0000

INDEXCOMP

Component index

0x03

0x0000

DIST

Distance register

0x03

0xFFFF

CAT

Category register

0x04

0xFFFF

AIF

Active Influence Field

0x05

0x4000

NID

Neuron Identifier

0x0A

0x0000

POWERSAVE

PowerSave

0x0E

n/a

FORGET

Forget

0x0F

n/a

NCOUNT

Count of committed neurons

0x0F

0x0000

RESETCHAIN

Points to the first neuron

0x0C

n/a

TESTCOMP

Test Component

0x08

0x0000

TESTCAT

Test Category

0x09

0x0000

The typical programming sequences to use the neurons are summarized below and described in detail in the

NeuroMem Technology Reference Guide.

https://www.general-vision.com/documentation/TM_NeuroMem_Technology_Reference_Guide.pdf

-Broadcast a vector to all the neurons (whether to learn or recognize it)

-Recognize the last broadcasted vector

-Learn the last broadcasted vector

-Save the content of all the neurons

-Read the content of a specific neuron

-Load the content of the neurons

NM500 Manual 7

2.1 NEURON REGISTERS IN DETAIL

Abbreviation

Normal mode

SR mode

NSR

Network Status Register

Bit[1:0], reserved

Bit[2], UNC (Uncertain)

Bit[3], ID (Identified)

Bit[4], SR mode

Bit[5], KNN classifier

The ID and UNC bits are updated

internally after each Write Last

Comp command.

ID is high if all firing neurons

report the same category.

UNC is high if several neurons fire

but disagree with the category.

Note that this is always the case if

the mode is KNN and 2 committed

neurons have different categories.

KNN is a recognition mode and

should not be active while

learning. Indeed, any pattern

would be recognized whatever its

distance from a neuron and the

learning will only create a single

neuron per new category.

Writing Bit 4 to 1 switches

the chain of neuron to SR

mode and points directly

to the RTL neuron.

GCR

Norm + Context and also

partial identifier of the RTL

neuron

Bit [6:0]= Context

Bit[7]= Lsup Norm

Bit[23:16]= Identifier[23:16]

Global Context assigned to all

neurons not already committed

If the Norm is not set to LSUP, the

default is the L1 Norn or

Manhattan distance.

Accessing the 3rd upper byte of the

RTL neuron is needed if the chain

of neurons is larger than 65535

neurons.

Read as 0xFFFF if the network is

full

N/A

MINIF

Minimum Influence Field

Global MINIF assigned to the non-

committed neurons

Read as 0xFFFF if the network is

full

MINIF of the pointed

neuron, assigned at the

time it was committed

MAXIF

Maximum Influence Field

Global MAXIF assigned to the non-

committed neurons

Read as 0xFFFF if the network is

full

N/A

NM500 Manual 8

Abbreviation

Normal mode

SR mode

NCR

Neuron Context Register

Bit[15:8]=0x00

Bit[7:0]= Identifier [23:16] of the

RTL neuron

Context of the pointed

neuron

Bit[15:8] = Identifier

[23:16]

Bit[7]= LSUP Norm

Bit[6:0]= Context [0, 127]

COMP

Component

Bit[15:8] = unused

Bit[7:0]= byte component

Each Write COMP stores the

component at the current

INDEXCOMP value and updates

the DIST register of the committed

neurons with NCR=GCR and also of

the RTL neuron. INDEXCOMP is

automatically incremented.

After each Read or Write,

moves to the next

INDEXCOMP of the

pointed neuron

LCOMP

Last Component

Bit[15:8] = unused

Bit[7:0]= byte component

Write LCOMP stores the

component at the current

INDEXCOMP value and updates

the DIST register of the committed

neurons with NCR=GCR and also of

the RTL neuron. INDEXCOMP is set

to 0.

The ID_ and UNC_ lines are

updated to report the recognition

status. If ID_ line is low, the

“identified category” is available

on the DATA bus.

N/A

INDEXCOMP

Component index

Common index pointing to

the neurons’ memory

between [0, 255].

Write INDEXCOMP moves to a

specific index value, but does not

reset the DIST register.

This value is incremented

automatically after each Read

COMP or Write COMP. It is reset

after a Write LCOMP.

NM500 Manual 9

Abbreviation

Normal mode

SR mode

DIST

Distance register

between [0, 65535]

DIST=0 means that the

vector matches exactly the

model of the firing neuron.

The higher the distance, the

farther the vector from the

model.

This register is updated by the

neuron during the broadcast of

components (Write COMP and

Write LCOMP)

Read DIST returns the distance of

the top firing neuron. This

“winner” neuron pulls out of the

race, so the next Read Dist will ne

answered by the next top firing

neuron, etc.

DIST=0xFFFF means that there are

no more firing neurons.

Must be read after Write LCOMP

and before Read CAT

N/A

CAT

Category register

Bit 15= Degenerated flag

(read-only)

Bits [14:0]= Category value

between 0 and 32766

(0x7FFE)

CAT greater than 32768

means that the responding

neuron is degenerated. The

value must be masked with

0x7FFF to report the

original category of the

neuron.

Write CAT of 0 does not commit a

new neuron, but may force

existing committed neurons to

reduce their influence fields.

Read CAT returns the category of

the top firing neuron

CAT=0xFFFF means that there are

no more firing neurons

Must be read after the DIST

low and the NID register does not

need to be read after the CAT

Category of the pointed

neuron

Read or Write CAT

automatically moves to

the next neuron index in

the chain.

AIF

Active Influence Field

This register is updated

automatically by all the firing

neurons during learning

operations (i.e. Write CAT)

Influence field of the

pointed neuron

NID

Neuron Identifier or index

of the neuron in the chain,

starting with the value 1

Bit[15:0]= 2 lower bytes of a

3-bytes neuron identifier.

The upper byte is stored in

the NCR register. Its access

is only necessary when the

chain of neurons is larger

than 65535.

This register is assigned

automatically when the RTL

neuron gets committed after a

Write CAT.

Read NID returns the identifier of

the firing neuron with the least

distance and least category. It

must be read after a Read CAT. (1)

Identifier of the pointed

neuron.

This register is assigned

automatically when the

pointed neuron gets

assigned a category

different from 0 with a

Write CAT.

NM500 Manual 10

Abbreviation

Normal mode

SR mode

POWERSAVE

PowerSave mode

Writing this register resets

the DATA lines to a tri-state

mode and ensures that they

do not draw current from

the pull-up resistors.

FORGET

Uncommit all neurons by

clearing their category

Note that the neuron’s memory is

not cleared, but its index is reset

to point at the first component.

Also reset the MINIF, MAXIF and

GCR to their default values.

N/A

NCOUNT

Count of committed

neurons

Bit[15:0]= 2 lower bytes of

the count

NCOUNT=0xFFFF means that all

neurons of the chain are

committed. If the chain of neurons

is greater than 65535 neurons this

can also means that 65535

neurons are indeed committed.

Reading the upper byte of the NCR

3 bytes value.

Index of the neuron

pointed in the chain.

Write RESETCHAIN points

to the first neuron. If it is

committed, NCOUNT will

be equal 1, otherwise 0.

RESET

CHAIN

N/A

Points to the first neuron

of the chain.

TESTCOMP(2)

For all committed neurons, write

their component pointed by the

current INDEXCOMP with the

same input value.

Refer to paragraph below for use

model.

TESTCAT(2)

Write the same category

to all the neurons. Useful

for test routines to commit

all neurons in one clock

cycle.

Refer to paragraph below

for use model.

(1) If the content of the neurons has been built using their model generator, there should be no occurrences

of firing neurons with the same distance and same category. As a result, reading the NID returns the

identifier of the sole firing neuron. If, on the contrary, the content of the neurons has been loaded in

Save-and-Restore and is such that multiple neurons can fire with the same distance and same category,

NID will return an “irrelevant” value which is the AND of all their identifier.

(2) Usage of the TEST registers: clear the neurons’ memory

-Write NSR 0x10 Set the SR mode

-Write TESTCAT 1 Commit all neurons with a dummy category value of 1

-Write NSR 0x00 Cancel the SR mode, back to normal mode

-For i=0 to 256

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