National Instruments 6584R Manuel utilisateur

NI 6584R User Guide and Specifications

The NI 6584 is an RS-485/422 adapter module designed to work in conjunction with your NI FlexRIO™

FPGA module. This document contains signal information and specifications for the NI 6584R,

comprised of an NI FlexRIO FPGA module and the NI 6584. This document also contains tutorial

sections that demonstrate how to generate and acquire samples using a LabVIEW FPGA example VI

and how to create and run your own LabVIEW project with the NI 6584R.

The NI 6584 comes in full duplex and half duplex versions, each with or without termination. The full

duplex version has separate RX (receive) and TX (transmit) pins for acquisition and generation,

respectively. The half duplex version performs either acquisition or generation on the same pin. The

unterminated versions of the full and half duplex devices are useful in multi-drop situations when you

are already using a terminated bus, and the terminated devices are useful in high-speed point-to-point

situations or as the terminated end points on a multi-drop bus.

Contents

Connecting Signals .............................................................................................................................. 2

Front Panel................................................................................................................................... 2

Cables........................................................................................................................................... 4

FPGA ........................................................................................................................................... 6

Using Your NI 6584R with a LabVIEW FPGA Example VI.............................................................. 7

Creating a LabVIEW Project and Running a VI on an FPGA Target ................................................. 9

NI 6584 Component-Level Intellectual Property ................................................................................ 12

How to Use Your NI FlexRIO Documentation Set ............................................................................. 14

Specifications....................................................................................................................................... 15

Where to Go for Support ..................................................................................................................... 18

Note Before configuring your NI 6584R, you must install the appropriate software and hardware.

Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation

instructions. Figure 1 shows an example of a properly connected NI 6584R.

Figure 1. NI 6584R

NI 6584 + NI FlexRIO FPGA Module = NI 6584R

NI 6584R User Guide and Specifications 2 ni.com

Connecting Signals

Front Panel

Figure 2 shows the Connector 0 (Ports 1–8) pin assignments for the NI 6584 in the full duplex

configuration. Connector 0 (Ports 1–8) is a 68-pin VHDCI connector that distributes its signals through the

NI VHDCI-to-Eight DB9 cable (197546-01) to the device under test (DUT). RX pins are acquisition

signals, and TX pins are generation signals. The full duplex configuration of the NI 6584 has individual

RX and TX pins.

Note The pinouts for Connector 0 are the same for both terminated and unterminated devices.

Figure 2. NI 6584 Connector 0 Pin Assignments (Full Duplex)

68 34

67 33

66 32

65 31

64 30

63 29

62 28

61 27

60 26

59 25

58 24

57 23

56 22

55 21

54 20

53 19

52 18

51 17

50 16

49 15

48 14

47 13

46 12

45 11

44 10

43 9

42 8

41 7

40 6

39 5

38 4

37 3

36 2

35 1

Connector 0 (Ports 0-8)

TX_6+

TX_7–

RX_7–

RX_6+

TX_7+

RX_6–

TX_6–

RX_7+

GND

TX_4+

TX_5–

RX_5–

RX_4+

TX_5+

RX_4–

TX_4–

RX_5+

TX_2+

TX_3–

RX_3–

RX_2+

TX_3+

RX_2–

TX_2–

RX_3+

GND

TX_0+

TX_1–

RX_1–

RX_0+

TX_1+

RX_0–

TX_0–

RX_1+

TX_14+

TX_15–

RX_15–

RX_14+

TX_15+

RX_14–

TX_14–

RX_15+

GND

TX_12+

TX_13–

RX_13–

RX_12+

TX_13+

RX_12–

TX_12–

RX_13+

TX_10+

TX_11–

RX_11–

RX_10+

TX_11+

RX_10–

TX_10–

RX_11+

GND

TX_8+

TX_9–

RX_9–

RX_8+

TX_9+

RX_8–

TX_8–

RX_9+

RS485/ RS422

Full Duplex

PFI

CONNECTOR 0 (PORTS 1-8)

CLOCK

NI 6584

©National Instruments Corporation 3 NI 6584R User Guide and Specifications

Figure 3 shows the Connector 0 (Ports 1–8) pin assignments for the NI 6584 in the half duplex

configuration. Connector 0 (Ports 1–8) is a 68-pin VHDCI connector that distributes its signals through

the NI VHDCI-to-Eight DB9 cable (197546-01) to the DUT. The half duplex configuration of the

NI 6584 places both the RX (acquisition) and TX (generation) signals on the same pins.

Note The pinouts for Connector 0 are the same for both terminated and unterminated devices.

Figure 3. NI 6584 Connector 0 Pin Assignments (Half Duplex)

Caution Connections that exceed any of the maximum ratings of input or output signals on the

NI 6584R can damage the device and the chassis. NI is not liable for any damage resulting from such

signal connections. For the maximum input and output ratings for each signal, refer to the

Specifications section of this document.

68 34

67 33

66 32

65 31

64 30

63 29

62 28

61 27

60 26

59 25

58 24

57 23

56 22

55 21

54 20

53 19

52 18

51 17

50 16

49 15

48 14

47 13

46 12

45 11

44 10

43 9

42 8

41 7

40 6

39 5

38 4

37 3

36 2

35 1

Connector 0 (Ports 0-8)

TX_6+/RX_6+

TX_7–/RX_7–

TX_7+/RX_7+

TX_6–/RX_6–

GND

TX_4+/RX_4+

TX_5–/RX_5–

TX_5+/RX_5+

TX_4–/RX_4–

TX_2+/RX_2+

TX_3–/RX_3–

TX_3+/RX_3+

TX_2–/RX_2–

GND

TX_1–/RX_1–

TX_0+/RX_0+

TX_1+/RX_1+

TX_0–/RX_0–

TX_14+/RX_14+

TX_15–/RX_15–

TX_15+/RX_15+

TX_14–/RX_14–

GND

TX_12+/RX_12+

TX_13–/RX_13–

TX_13+/RX_13+

TX_12–/RX_12–

TX_10+/RX_10+

TX_11–/RX_11–

TX_11+/RX_11+

TX_10–/RX_10–

GND

TX_9–/RX_9–

TX_8+/RX_8+

TX_9+/RX_9+

TX_8–/RX_8–

RS485/ RS422

Half Duplex

PFI

CONNECTOR 0 (PORTS 1-8)

CLOCK

NI 6584

NI 6584R User Guide and Specifications 4 ni.com

Cables

Figure 4 shows the NI VHDCI-to-Eight DB9 cable (197546-01) connected to the NI 6584 at

Connector 0 (Ports 1–8) and then fanning out to display each of its eight, nine-pin port connectors.

Figure 4. NI 6584 and NI VHDCI to Eight DB9 Cable

1 NI 6584 adapter module 2 NI VHDCI to Eight DB9 cable (197546-01)

PORT

1 2

©National Instruments Corporation 5 NI 6584R User Guide and Specifications

Tables 1 and 2 show the pin assignments for each of the eight port connectors on the

NI VHDCI-to-Eight DB9 cable. Two channels are assigned to each port.

Note The pinouts for the port connectors are the same for both terminated and unterminated devices.

Table 1. Pin Assignments on Each Port (Full Duplex)

Connector Pin Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8

1GND GND GND GND GND GND GND GND

2RX_1+ RX_3+ RX_5+ RX_7+ RX_9+ RX_11+ RX_13+ RX_15+

3TX_1+ TX_3+ TX_5+ TX_7+ TX_9+ TX_11+ TX_13+ TX_15+

4RX_0+ RX_2+ RX_4+ RX_6+ RX_8+ RX_10+ RX_12+ RX_14+

5RX_0– RX_2 RX_4– RX_6– RX_8– RX_10– RX_12– RX_14–

6RX_1– RX_3– RX_5– RX_7– RX_9– RX_11– RX_13– RX_15–

7TX_1– TX_3– TX_5– TX_7– TX_9– TX_11– TX_13– TX_15–

8TX_0+ TX_2+ TX_4+ TX_6+ TX_8+ TX_10+ TX_12+ TX_14+

9TX_0– TX_2– TX_4– TX_6– TX_8– TX_10– TX_12– TX_14–

GND = Ground

Table 2. Pin Assignments on Each Port (Half Duplex)

Connector Pin Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8

1GND GND GND GND GND GND GND GND

2NC NC NC NC NC NC NC NC

3TX_1+/

RX_1+

TX_3+/

RX_3+

TX_5+/

RX_5+

TX_7+/

RX_7+

TX_9+/

RX_9+

TX_11+/

RX_11+

TX_13+/

RX_13+

TX_15+/

RX_15+

4NC NC NC NC NC NC NC NC

5NC NC NC NC NC NC NC NC

6NC NC NC NC NC NC NC NC

7TX_1–/

RX_1–

TX_3–/

RX_3–

TX_5–/

RX_5–

TX_7–/

RX_7–

TX_9–/

RX_9–

TX_11–/

RX_11–

TX_13–/

RX_13–

TX_15–/

RX_15–

8TX_0+/

RX_0+

TX_2+/

RX_2+

TX_4+/

RX_4+

TX_6+/

RX_6+

TX_8+/

RX_8+

TX_10+/

RX_10+

TX_12+/

RX_12+

TX_14+/

RX_14+

9TX_0–/

RX_0–

TX_2–/

RX_2–

TX_4–/

RX_4–

TX_6–/

RX_6–

TX_8–/

RX_8–

TX_10–/

RX_10–

TX_12–/

RX_12–

TX_14–/

RX_14–

GND = Ground

NC = No connect

NI 6584R User Guide and Specifications 6 ni.com

FPGA

Table 3 lists the NI 6584 connector signals and the corresponding NI FlexRIO FPGA module signals necessary for designing a custom

component-level IP (CLIP). Channel 0 and Clock I/O are global clocks. The _CC suffix on the RX Data signals identifies channels that are capable

of receiving a regional clock. Refer to the Virtex-5 FPGA User Guide at www.xilinx.com for more information about regional clocks on your FPGA.

Table 3. NI 6584 Connector Signals and NI FlexRIO FPGA Module Signals

NI 6584 NI FlexRIO FPGA Module

Connector Signal Name TX Data

TX Data

Bank

TX Data

Enable

TX Data

Enable Bank RX Data

RXData

Bank

RX Data

Enable

RX Data

Enable Bank

Connector 0

(VHDCI)

Channel 0+/– GPIO_21 1GPIO_1 0GCLK_SE —GPIO_18 1

Channel 1+/– GPIO_22 1GPIO_14 0GPIO_7_CC 0GPIO_14_n 0

Channel 2+/– GPIO_8 0GPIO_12 0GPIO_23_CC 1GPIO_27 1

Channel 3+/– GPIO_9 0GPIO_13 0GPIO_24_CC 1GPIO_29 1

Channel 4+/– GPIO_54 3GPIO_60 3GPIO_39_CC 2GPIO_61 3

Channel 5+/– GPIO_43 2GPIO_47 2GPIO_40_CC 2GPIO_65 3

Channel 6+/– GPIO_52 3GPIO_51 3GPIO_37_CC 2GPIO_35 2

Channel 7+/– GPIO_53 3GPIO_63 3GPIO_38_CC 2GPIO_46 2

Channel 8+/– GPIO_19 1GPIO_16 1GPIO_5_CC 0GPIO_17 1

Channel 9+/– GPIO_20 1GPIO_29_n 1GPIO_6_CC 0GPIO_30 1

Channel 10+/– GPIO_10 0GPIO_2 0GPIO_25_CC 1GPIO_3 0

Channel 11+/– GPIO_11 0GPIO_28 1GPIO_26_CC 1GPIO_28_n 1

Channel 12+/– GPIO_55 3GPIO_35_n 2GPIO_58_CC 3GPIO_36 2

Channel 13+/– GPIO_44 2GPIO_48 2GPIO_59_CC 3GPIO_64 3

Channel 14+/– GPIO_41 2GPIO_49 3GPIO_56_CC 3GPIO_50 3

Channel 15+/– GPIO_42 2GPIO_62 3GPIO_57_CC 3GPIO_45 2

BNC Clock I/O GPIO_16_n 1GPIO_17_n 1GCLK_LVDS — — —

BNC PFI GPIO_0 0GPIO_1_n 0GPIO_4_CC 0 — —

©National Instruments Corporation 7 NI 6584R User Guide and Specifications

Using Your NI 6584R with a LabVIEW FPGA Example VI

The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get

you started creating your LabVIEW FPGA program. This section demonstrates how to use an existing

LabVIEW FPGA example project and a basic universal asynchronous receiver/transmitter (UART)

interface to perform serial generation and/or acquisition with the NI 6584R. This example requires an

NI VHDCI-to-Eight DB9 cable. If you are operating an unterminated device, NI recommends that you

use external termination.

Note Examples available for your device are dependent on the device-specific minimum software

requirements. For more information about the minimum software requirements for your device, visit

ni.com/info and enter rdsoftwareversion as the Info Code.

Each NI 6584R example project includes the following parts:

• A LabVIEW FPGA VI that can be compiled and run embedded in FPGA hardware

• A Host VI that runs in LabVIEW for Windows and interacts with the LabVIEW FPGA VI

Note In NI application software, NI FlexRIO adapter modules are referred to as IO Modules.

Complete the following steps to run an example that generates and/or acquires data.

1. Connect the VHDCI end of an NI VHDCI-to-Eight DB9 cable to Connector 0 (Ports 1–8) on the

NI 6584R.

2. Connect the Port 1 DB9 connector from the NI VHDCI-to-Eight DB9 cable to the DUT with

proper termination.

Note This exercise shows how to complete these tasks for the full duplex version of the NI 6584. To

complete these tasks with a different hardware version of the NI 6584, replace every instance of Full

Duplex in these instructions with Half Duplex, Full Duplex No Termination, or Half Duplex No

Termination,depending on which device you are using.

3. Launch LabVIEW.

4. In the Getting Started window, select Find Examples to display the NI Example Finder.

5. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»IO Modules»

NI 6584.

6. Select NI 6584 Basic Software UART Full Duplex.lvproj.

7. In the Project Explorer window, double-click NI 6584 Basic Serial UART Full Duplex

(Host).vi under My Computer. The host VI opens. This VI uses the NI 7952R as the FPGA target

by default. To use the NI 6584, complete the following steps to change the FPGA target.

Note All example projects are configured for RIO0. If your device is not named RIO0 (verify in

MAX), you must update the target device name by right-clicking your device in the Project

Explorer window, selecting Properties, and entering the correct target device name in the Resource

control.

a. Select Window»Show Block Diagram to open the VI block diagram.

b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R) function and

select Configure Open FPGA VI Reference.

c. In the Configure Open FPGA VI Reference window, click the Browse Project button in the

Open VI section.

d. In the Select VI window that opens, expand the tree view for your device, select the VI under

your device and click OK.

NI 6584R User Guide and Specifications 8 ni.com

e. Click OK in the Configure Open FPGA VI Reference window.

f. Save the VI.

8. On the front panel, complete the following steps to generate data.

a. Enter data into the Gen Data (Hex) control. This displays the data to be generated in

hexadecimal format.

b. Set the Gen Data Width control to a number between 1 and 32. The default is 8.

c. Set the Stop Bits control to a number between 1 and 65,535. The default is 1.

d. Set the Gen Clock Divider control. The default generation rate of the UART is 16 Mbit/s, but

it is capable of running at any integer division of this rate. For example, to generate at a rate

of 9,600 Kbit/s, set the Gen Clock Divider to 1,667. (16 Mbit/s divided by 1,667 clock cycles

produces a clock rate of 9,598 Kbit/s.)

e. To generate data continuously, leave the Write Data control enabled. To stop generation, click

the Write Data button.

9. On the front panel, complete the following steps to acquire data.

a. Set the Acq Data Width control to a number between 1 and 32. The default is 8.

b. Set the Samples to Acquire control to a number between 1 and 1,023. The default is 5.

c. Set the Acq Clock Divider. The default acquisition rate of the UART is 16 Mbit/s, but it is

capable of running at any integer division of this rate. For example, to acquire at a rate of

9,600 Kbit/s, set the Acq Clock Divider to 1,667. (16 Mbit/s divided by 1,667 clock cycles

produces a clock rate of 9,598 Kbit/s.)

d. To acquire data continuously, leave the Read Data control enabled. To stop acquisition, click

the Read Data button.

Note If you are using the half duplex version of the NI 6584R, you cannot both acquire and generate

data at the same time. You must choose whether to enable the Write Data button or the Read Data

button.

10. Click the Run button to run the VI. The NI 6584R generates and/or acquires data on Channel 0 of

Port 1. If a timeout error occurs, the number of samples acquired did not reach the value specified

in the Samples to Acquire control.

Figure 5 shows the front panel controls and indicators configured for generating and acquiring data in

this example VI. Close the VI when you are finished generating and acquiring data.

Figure 5. NI 6584 Basic Serial UART Full Duplex (Host) VI Front Panel

Creating a LabVIEW Project and Running a VI on an FPGA Target

This section demonstrates how to create a LabVIEW project, an FPGA VI, and a host VI that writes and

reads data on the NI 6584R. This exercise also demonstrates how to compile the FPGA VI on your target

and run a VI on the host machine. This exercise shows how to complete these tasks for the full duplex

version of the NI 6584. To complete these tasks with a different hardware version of the NI 6584, replace

every instance of Full Duplex in these instructions with Half Duplex, Full Duplex No Termination, or

Half Duplex No Termination,depending on which device you are using.

Note Disconnect all signals from the NI 6584R connectors before running this VI.

Creating a Project

1. Launch LabVIEW.

2. In the Getting Started window, select Empty Project. The new project opens in the Project

Explorer window.

3. Save the project as Data RW.lvproj.

NI 6584R User Guide and Specifications 10 ni.com

Creating an FPGA Target VI

1. In the Project Explorer window, right-click My Computer and select New»Targets and

Devices.

2. In the Add Targets and Devices on My Computer window, select the Existing Target or Device

radio button and expand the FPGA Target. The target is displayed.

3. Select your device and click OK. The target and target properties are loaded into the project tree.

4. In the Project Explorer window, right-click the FPGA target and select New»VI. A blank VI

opens.

5. Select Window Show»Block Diagram to open the block diagram window.

6. In the Project Explorer window, select FPGA Target (RIOx, PXI-79xxR).

7. Right-click IO Module and select Properties. In the General category, you can see the available

component-level IP (CLIP) for the NI 6584 in the Component Level IP pane. If the category

information is dimmed, select the Enable IO Module checkbox.

Note For more information about CLIP for the NI 6584, refer to the NI 6584 Component-Level

Intellectual Property section of this document.

8. Select NI 6584 Full-Duplex to configure the software for the full duplex version of the NI 6584R.

9. Select NI 6584 Basic Connector to use the connector-based CLIP. Click OK.

10. In the Project Explorer window, select IO Module (NI 6584 Full-Duplex : NI 6584 Basic

Connector).

11. Select RX, TX, and TX_Enable and drag them onto the block diagram.

12. Add a While Loop around the three Data nodes.

13. Wire an indicator from the output of the IO Module\RX.

14. Wire a control to the input of the IO Module\TX.

15. Wire a numeric constant to the input of the IO Module\TX_Enable node. Set the value to 65,535.

(This enables all 16 TX channels like 0xFFFF in hexadecimal.)

16. Wire a False constant to the stop condition of the While Loop.

Your block diagram should now resemble the block diagram in Figure 6.

Figure 6. Data RW (FPGA).vi Block Diagram

17. Save the VI as Data RW (FPGA).vi.

18. Close the VI.

19. In the Project Explorer window under My Computer, expand the tree view for your device,

right-click Data RW (FPGA).vi and select Compile to compile the files for your target.

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