Nakamichi 530 Manuel utilisateur

Service

Manual

Nakamichi

530

Receiver

CONTENTS

1.

General

«-

ete

ce

cc

ee

te

ee

eee

eet

eee

tee

we

eet

eee

tee

tees

3

2.

Principle

of

Operation

-

+--+

0

eee

eect

eee

tt

cee

ee

eee

ee

eet

eee

rete

tee eee

4

2.

Fundamental!

Circuits

«++.

0

eee

eet

eee

et

ee

eee

e

ee

teens

Wok

gaa

oti

Seve

Ss

wae kes

4

BAAS.

HONOS

AG

ok

hs

bea

ated

bY

Gee.

ain

ence

ag

Rundeativa

woken

esd

ante

mi

wpe

indie

ira

Oe

4

(1)

Features

of

CMOS

IC

--

eee

cece

ence

eee

dcp

kua

tebe

ares

keke

seawake

4

(2)

Gate

Logic

oes

erect

cece

eee

ee

eee

ete

ee

eee

e

tenes

5

(3)

Gated

Flip-Flop

bite

Neier

eines

&

seidy

yaa

BeS,

Risen

aeres

oS

ate

lo

Lesan

a

Neva

eoras

aie

Taree

eta

en

Cred

ORME

a

ON

a

ere,

ele

anueee

5

(4)

Compatible

CMOS

ICs

---+--

esse

cece

eee

te

eee

ete

teen

ees

5

2.1.2

Operational

Amplifier

IC...

-

eee

cece

eee

nee

teeter

eee

tees

6

(1)

Voltage

Follower

Circuit

---

+--+

e

cece

ree

ec

cee

ee

eee

eee eee

teen

een

n

eee

6

(2)

Amplifier

Circuit

--

+.

eee

cee

ee

nee

ee

cn

cere

ete

ee

teen

eees

6

(3)

Oscillator

(Astable

Multivibrator)

«---

+e

e

sec

e

eee

cere

eee

renee

eee

tence

6

(4)

Peak

Holding

Circuit

--

+

eee

ce

eee

ce

eee

rete

tenes

7

2.1.3.

Quadrature

Detector

-----

eee

crete

etcetera

eet

e

eee

ee

tet

ee

eeee

7

2. 2.

Power

Mute

Signal

-+

++.

secre

cece cece

eee

te

tee

ete

et

eee

tee

tenes

8

2,

3.

TUMEr

SECTION:

-rs

eterna.

Speeie

te

Dw

Reales

sate

eee

eye toe

Soe

ela ele Wow

enw

Sl

eat

e 8

Calais

arate

te

ete

ysl

ORNS

“Sue

Usa

9

2.3.1.

FM

MPX

Stereo

Broadcasting

Operation

.....---

eee

e

eee

ee

eee

ete

ee

tee

eens

9

2.3.2.

Operation

of

Tuner

Section

©...

6c

cece

ee

ete

eee

teen

teenies

10

2.3.3.

Tuning

System

0.

ee

eee

e

eee

eteeet

eee

e

eee

ene

eee

een

tte

eee

n

nee

11

(1)

Varicon

Voltage

..--

ee

ccc

cere

eee

tee

eet

erent

eee

tenes

11

(2)

Motor

Drive

Circuit

and

Frequency

Sensor

...---

+e

seer

eee

11

(3)

Preset

Tuning

«++.

ee

eee

ee

eee

ee

tee

eee

tee

te

ee

eee

tte

12

(4)

Station

Detecting

Circuit

©...

6...

cece

eee

te

eens

13

(5)

Auto-TUning

«-

eee

ccc

recente

tee

eee

ete

eee

13

(6)

Tuning

Indicator...

6.

eee

cece

eee

ene

15

(7)

FM

Mute

and

Compulsion

Mono

«+...

+e.

eee

cece

eee

ete

eee

e

eet

n

ene

17

9:

9A.'=

.Rinplitier

SROOM:

att

sc

¢

tices

pes

8G

Kee

ORE

MRE

a

tec

decal

ee

wedi

ead

18

2.4.1.

Phono

Eq.

Amplifier

----

2-2

ee

eee

cee

te

ete

ee

crete

teeter

eee

18

2.4.2,

Subsonic

Filter

«6...

22

ccc

cece

cere

c

ccc

tcc

e

eee

rece

nee

e

eset

seen

ease

eeeeenes

19

2.4.3.

Tome

Control

2...

-

2c

ccc

cc

cece

c

tence

eee

teen

rene

erate

eee

renee

enee

20

2.4.4.

Power

Amplifier...

--

0

eee

cece

eee

te

ee

eer

e

teen

ena

21

(1)

Pre-stage

(Voltage

Amplifier)

..

1.26.0.

e

cece

ce

eee

ee

beeen

teens

21

(2)

Output

Stage

(Power

Amplifier)

.

2...

00.

cece

ete

eee

ees

21

4(3))

CLithiter:

<setceatoiee

aretting

ve

a

eS

Saleh

de

a

EA

ee

ea

Lele

ee

ae

23

24.5.

Protector

Circuit

«2.

2

cen

ee

cece

ee

eee eae

ened

ee

een

ee

eee

ae

en

eee

24

3:

“Removal

Procedures®

+«.:/..2

6s

:c.c505

eo

et

ke

eee

ee

eee

re

eee

Sele

ewe

aa

a

Ete

ead

eel

ere

BUN

ene

dee

ee

25

Ke

1.

Top

Cover

a

See

eee

et

ee

ar

ee

er

a

ee

eer

ee

eR

eee

ee

PC

CR

Oa

Pr

Tee

Dar

Oe

Meroe

Sa

Ma

et

Dae

Ta

25

3.2.

Bottom:

COVer:

acces

cc2

5

cera

ade

eae

BN

Re

hele

wha

he

Aerie

a

yaad

eS

jane

se

aes

Bia

e

Ol

Sie

a

Heese

25

3:3:

Front

Panel

Ass’y

ids

Wane

teas

ec

ek

peietiol

tes

ciao

Vaaen

wa

in

Sue

Oan

tek

Ee

ga

9

25

3.

4.

Front-end

Holder

Ass’y

.--

2

eee

cece

eee

ee

cee

eee

ete

25

3.

5.

Power

Transformer...

see

cece

te

eee

eet

ee

eee

ee

eee

tee

eee

ee

eens

25

3.

6.

Diode

Bridge

---

+.

eee

ee

eee

ee

ete

teen

teens

25

Ol.

CLs

Power

P.C.B.

Ass’y

and

Heat

Sink...

.-

eee

ee

eee

ee

eee

ete

tee

ee

ete

eens

25

3.

8.

Pulley

Holder

B

Ass’y

and

Pulley

Ass’y

«2.

-

eee

cece

eect

erence

ere

rete

eee

e

tenes

25

3.

9.

Front

Chassis

Ass’y

--

20

-e

cece

ee

eee

re

eee eee

eee

teeta

ene

25

3.

10.

Scale

Holder

Ass’y

-

eee

er

cece

ee

eee

ete

tee

ete

nee

ete

neee

25

3.

11.

Lamp

House

Cover

Ass’y

and

Lamp

P.C.B.

Ass’y

--

sees

cece

eee

e

eee

nee

26

3.

12.

Tuning

Lamp

P.C.B.

Ass’y

+e

eee

e

cece

cere

ene

cere

e

tee

e

eee

eenees

26

3.

13.

Indicator

P.C.B.

Ass’y

-

+.

ee

eee

cere

eee

ete

eee

ee

erence

eee

tenets

26

3.

14.

Tuning

Control

Switch

Ass’y

---

2

eee

tee

eee

ee

teen

eet

tee

27

3.

15.

|

Auto-Tuning

P.C.B.

Ass’y,

Preset

Volume

P.C.B.

Ass’y

and

Preset

Switch

P.C.B.

Ass’y

+--+

ese

etree

eee

ee

eee

tenes

ee

27

3.

16.

Power

SWitch

=.

6622s

cee

wee

ee

ec

cc

eee

ee

et

meee

eee

eens

ede

e

eens

27

3.

17.

Main

P.C.B.

Ass’y

and

Function

P.C.B.

Ass’y

«++.

eee

cree

eee

eens

27

3.

18.

Headphone

Jack

«2...

cece

eee

cent

ee

nee

teeta

teen

eens

27

3.

19.

Rear

Panel

Ass’y

+

eee

ee

eee

te

eer

ee

tee

ee

tee

eee eee

ete

t

etter

tenes

27

3.

21.

BC

Outlet

ie

5

ois

hee

te

ak

es

SR

ee

Rule

een

ee

eS

wae

eS

Pee

eee

B54

BEE

Sree

are

g

eR

ee

AS

28

3.

22.

Motor

Base

Ass’y,

Front-end

Pulley

and

Front-end

«---

esse

tee

e

creer

eee

eet

eens

28

4.

Adjustments

and

Measurements

----

<0

-

eee

ret

ee

ene

te

eee

tenet

ete

tenets

29

4,

1.

FM

Tuner

Section

--

0.

ee

cece

ree

nee

eee

ett

ee

eee

ee

eee

29

4.1.1.

Electrical

Adjustments

and

Measurements

----

+--+

e

eter

terete

eee

teens

29

4.1.2.

Auto-Return

Scale

Calibration

--

+--+

eee

e

ee

eee eee

eee

eens

da

Rik

tagetaneee

cybiarte

etenshecensiteteaie

8

34

4.

2.

Preamplifier

Section

-----

eee

cette

eee

tect

e

tenet

e

eee

c

eee

eens

34

4.2.1.

Signal-to-Noise

Ratio

Measurement

«+++

ese eee

reece

eee

renee

eee

t

eee

e

eee

eres

34

(1)

Phono

Input/Recording

Output

-----se

eee

reece

tee

eet

tee

eee

eens

34

(2)

Aux.

Input/Preamp.

Output

.--

+--+.

eee

t

eee

e

nents

34

4.2.2.

Distortion

Measurement

.--

eee

cree

eter

ee

ree

ete

ee

eet

tee eee

nen

ete

34

(1).

Phono

Input/Recording

Output

----

+.

eee

cect

nce

eee eee

eee

nee

34

42}

Aux.

Input/Preamp.

Qutput

(<6

+4s

esos

nrews

weeks

node

ease

eh

inet

IN

esos

wee

34

4.2.3.

Phono

Eq.

Amp.

DC

Offset

Adjustment

-----

seer

cere

cree

eee

tenet

e

ene

35

4,

3.

Power

Amplifier

Section

-------

cette

tee

ete

te

teen

tenet

e

nent

nett

ee

eens

35

4.3.1.

Idling

Current

Adjustment

+--+

esses

ee

tee

cece

cee

ete

te

tte

tenet

eee

tents

35

5.

Dial

Threading

and

Scale

Calibration

©.

+--+

+e

ee

ctr

te

ee

eee

ett

teen

eens

36

5.

1.

Dial

Threading

pach

eat

a

eS

th

ae

ny

SY

Nee

OR

ne

|

Be

oes

orca

cca

a

rerea

ie

Aue

Brave

le

Gia,

Use

D

we

letare

exah

gua

aeneay

ee

36

5.1.1.

How

to

prepare

dial

thread

-----

ee

erect

eee

ett

eee

tet

eee

36

5.1.2.

How

to

set

dial

threading

---

+--+

ester

rete

ee te

tee

ett

ee

ene

ete

teen

ete

36

5.

2.

Scale

Calibration

--

000

cece

tee

ee

eee

ee

ete

eee

teeta

eee

36

6.

Mounting

Diagrams

and

Parts

List

-.----

02-2

s

eect

eee

treet

ee

en

teen

ete

n

ea

eee

nee

37

6.

1.

Main

P.C.B.

Ass’y

ee ee

eee

ce

teeter

tee

ete

ee

eet

enter

ee

tte

37

6.

2,

Power

P.C.B.

Ass'y

selidhaa

Vou

ded

Toca

(EP

aon

acto

Boke,

vo

Tote

bh

guta

Roiestinies

eesceieston

WS

Cace

aretlss

See

Grids.

d

oM

eboney

da

eneoatare

re:

ee

39

6

3.

Lamp

P.C.B.

Ass'y

cere

cee

ete

ee

tee

ene

t

eee

ee

eee

en

ete

ee

eee

39

6.

4.

Preset

Switch

P.C.B.

Ass’y

eee

cere

cert

tee

terete

eterna

te

teen

eee

erate

41

6.

5,

Auto-Tuning

P.C.B.

Ass’y

cere

eee

ete

cette

een

n

teen

entre

renee

ete

nets

41

6.

Preset

Volume

P.C.B.

ASS’y

+e

eter

ete

teeter

tee

tence

tate

teen

ene

41

6.

7.

Indicator

P.C.B.

ASS’Y

+

eee

eet

tree

erect

eee

teen

eee

tte

e

seen

esate

41

6.

8

Function

P.C.B,

ASS'Y

cece

ect

rteeereree

eee

ee

ene

tennant

nent

ene

te

ene

41

7.

Mechanism

Ass’y

and

Parts

List

-

+--+.

+e

terete

ee

tet

e

ee

eee

tet

teen

ene

42

7.

1.

SYNTHESIS

«eee

ee

eee

ene

teen

eee

eta

42.

73.

<2,

Front

Panel

Ass’y

(AQ1)

«0

-

see

cece

ete

ee

tere

teen

tenet

ee

eee

e

ene

tenn

es

43

7.

3.

Synthesis

Mechanism

530

(AOQ2)

«sss

ere

t

ttt

terete

ttre

treet

ete

eee

etree

44

7.

4.

Front

Chassis

Ass’y

(BO1)

ser

cece

cre

crc

ete

e

eet

r

ree

teen

ete

e

een

e

tee

e

nen

cnet

es

45

7.

5.

Main

Chassis

Ass’y

(BO2)

-+

++

ec

ect

t

ete

terete

tere

et

eee een

e

cnet

e

eee

tenets

46

7.

6.

Rear

Panel

Ass’'y

(B03)

«sss

ttc

ctr

tt

terre

terete

ete

teen

eet

treet

een

ee

tenes

47

Te Ts

Tuning

Control

Switch

(CO1)

--

errr

ttre

tt

erent

ete

tet

teen

en

cess

48

Y

ee

Scale

Holder

Ass’y

(CO2)

-

secre

reece

etter

te

ttt

ee

eee

ete

49

7.

9.

Power

Block

Ass’y

(DOT)

++

secrete

ttt

etree

teeter

te

ete

e

eee

ete

eaten

een

tees

50

7.

10.

Front-end

Holder

Ass’'y

(DO02)

«s+

eset

etre

tert

teeter

ee

ttre

eee

ens

51

7.11.

Lamp

Case

Ass’'y

(EOI)

sect

cece

rte

teeter

ener

t

teen

enter

eee

nets

51

7.

12.

Lamp

House

Cover

Ass’y

(EO2)

--

+s

sec

c

rrr

etter

rere

r

terete

teeter

tenes

52

7.

13.

Lamp

Base

Ass’y

(EO3)

«s+

reer

rer

cre

ttt

tt

tet

tee

tnt

ete

teeta

e

eee

ene

ees

52

7.

14.

Motor

Base

Ass’y

(FO)

<cre

tere

terete

tee

teen

tet

eee

n

een

n

eee

n

een

entre

52

8.

Block

Diagrams

Sih

Redciimias

ei

eta!

Soe

secie.

Gem

rlonh,

dowrats

seca

fevtocaan

hema

tetas

Brak;

SMA

Oh

Beat

ees

Whe.

Wiens

weld!

eceteniay

ai

teh

tellettay

gal

Tercera:

ietgee

nat

See

53

8.

1.

Tuning

Section

«secre

crete

rete

r

ee

eeeeet

tet

e

en

teeter

eee

e

ects

53

8.

2.

Amplifier

Section

-:

++

+c

scree

eee

tee

eee

eter

t

etn

n

seen

eee

ene

54

9.

Performance

Data

«+--+

-

sce

t

eee

cette

teen

ee

ener

te

teen

ee

eet

ee

55

9.

4.

Tuner

Section

«sere

ere

ee

tt

tee

ete

eee

nee

ene

eee

eet

e

eater

eae

ee

see?

55

9.

2.

Amplifier

Sections:

+e

treet

errr

teen

tenet

entree

etn

e

tenant

este

en

nent

55

10.

Schematic

Diagram

Basin

bs

etd

he

Teco?

6

Resse

bP

aa

es

pre

BSN

cee!

ain

See

w

eie

a

cote

Let

pe

Gace

Sy

a

ene

B.S

sree

tan

ernie

Te

Ge

te

ees

a

ae

55

V1.

Wiring

Diagram

«+++

-

0

ee

eee

ees

bh,

Jetset

ou

cate

iuwatd

saebetacin

dy

thcevd

bch

tne

ce

eto

acer

es

57

12,

Specifications

---

++

ce

eet

eee

tet

ee

tte

een

ete

e

eee

ert

e

eae

tere

ee

ete

58

3.

20.

12P

Jack,

Speaker

Terminal

and

Antenna

Terminal

-

+--+.

sees

cere

eter

ee

eee

tren

ee

eens

27

1.

GENERAL

Nakamichi

530

control

functions

are

shown

below:

Pe

Totss

150

Watts

Max,

8)

64

on

)

ONoOkANnNr-oo

ONAaAPWN>

Nakamichi

530

Receiver

-Mopet

No.

$30

Voltages

120V

~

‘Unit

Pewer

‘AC

Outlets

Total

Subsonic

Filter

Switch

Mono

Switch

Loudness

Switch

Audio

Mute

Switch

FM

Mute

Switch

Hi-Blend

Switch

Threshold

Selector

Switch

Tuning

Pointer

Tuning

!ndicators

.

Tuning

Scale

.

Stereo

Indicator

FM

Muting

Indicator

.

Power

Switch

.

Speaker

Selector

Switches

.

Station

Preset

Controls

.

Automatic

Scanning

Switches

.

Station

Memory

Switches

Volume

Control

@)

&@

9)

Antenne

3000tm

Bai.

7EohmUnbel.

SCenenriios

ys

Ve

ey

ae

‘3bOWatte

Max.

ate

he

be

~

wey

gH

63)

62)

102

104

106

tebe

tr

tbs

te

dad

Fig.

1.1

Front

View

Fig.

1.2

Rear

View

Spaskars:

(tenet

@eo

O16

A

4 ;

A

19.

20.

21.

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

32.

33.

34.

35.

©

Ben

anie

69)

@9

Moe

e4)

Balance

Control

Tone

Controls

(Bass,

Treble)

Tape

Monitor

Switch

Function

Selector

Switches

(Aux/FM/Phono)

Headphone

Jack

Ground

Terminal

Phono

Input

Jacks

Auxiliary

Input

Jacks

Tape

Playback

Input

Jacks

Tape

Recording

Output

Jacks

Preamplifier

Output

Jacks

Main

Amplifier

Input

Jacks

Speaker

Output

Terminals

(A

&

B)

75-ohm

Unbalanced

Terminals

300-ohm

Balanced

Terminals

AC

Outlets

AC

Power

Cord

2.

PRINCIPLE

OF

OPERATION

2.1.

Fundamental

Circuits

2.1.1.

C-MOS

IC

(1)

Features

of

C-MOS

IC

The

IC’s

used

in

the

logic

circuit

of

the

N-530

are

of

the

C-MOS

{complementary

metal

oxide

semiconductor)

type,

in

which

P-channel

and

N-channel!

MOS

FET’s

complement

each

other.

(a)

Small

power

consumption

A

C-MOS

is

an

inverter,

as

shown

in

Fig.

2.1.1.

Whether

the

input

of

this

inverter

is

at

H

or

L

level,

either

the

P-channel

or

N-channel

MOS

FET

is

OFF,

and

therefore,

current

does

not

pass

from

VDD

to

VSS

under

steady

normal

state.

Consequently,

when

there

is

no

input,

power

consumption

(VDD

x

!DD)

is

nearly

zero,

except

for

surface

and

junction

leakage.

When

the

input

signal

is

switched

from

H

to

L,

or

Lto

H,

however,

both

P-

and

N-channel

FET’s

instantly

come

on,

and

a

current

flows

either

charging

or

discharging

the

stray

output

capacity,

so

that

the

power

consumption

during

dynamic

operation

cannot

be

said

to

be

zero.

(b)

A

large

noise

margin

The

input-output

transmission

characteristics

of

the

C-MOS

inverter

differ

from

those

of

bipolar

IC's

as

shown

in

Fig.

2.1.2.

The

knee

characteristic

is

sharper,

the

threshold

voltage

is

almost

half

of

VDD,

and

the

output

amplitude

is

nearly

equal

to

VDD

—

vss.

Since

the

noise

margin

of

a

digital

IC

is

defined

as

the

difference

between

the

minimum

value

of

output

amplitude

and

the

required

minimum

amplitude

of

the

input

signal,

it

is

quite

natural

that

the

C-MOS

circuit,

which

produces

an

output

amplitude

of

nearly

VDD

—

VSS

and

should

be

operated

by

a

small

input

signal,

should

have

a

large

noise

margin.

(c)

High

input

impedance

A

C-MOS

IC

has

a

very

high

input

impedance

because

it

is

insulated

from

the

substrate

by

the

oxide

film

of

the

gate.

Although

leakage

resistance

must

be

considered

in

an

actual

C-MOS

IC

because

diodes

are

usually

used

in

the

direction

of

reverse

bias

for

protecting

input

circuit,

its

impedance

is

several

tens

of

megohms.

The

advantage

of

a

high

input

impedance

is

that

the

fan-out

of

the

IC

is

large,

which

simplifies

the

interface.

Also,

a

timer

circuit

for

a

longer

‘period

of

time

can

be

produced.

This

means

that

the

high

input

impedance

enables

the

input

to

be

connected

with

a

large

resistance,

but

does

not

mean

to

use

a

capacitor

of

large

capacity.

(d)

Wide

operating

voltage

range

Fig.

2.1.3

shows

input-output

transfer

characteristics

of

C-MOS.

The

general

purpose

C-MOS

family

has

a

wide

operating

voltage

range

extending

from

3

to

18V,

which

is

much

wider

than

that

of

TTL

and

DTL

(5+

0.25

V),

and

HTL

(15

+

1.5

V).

The

reason

for

the

C-MOS

IC’s

wide

operating

voltage

range

is

that

the

P-MOS

and

N-MOS

are

made

symmetrical,

and

if

VDD

is

varied,

the

threshold

voltage

for

the

circuit

is

always

about

half

of

VDD.

Ina

bipolar

IC,

the

threshold

voltage

is

decided

by

the

forward

voltage

from

the

base

to

the

emitter

of

the

transistor

(VBE),

and

is

little

affected

by

the

source

voltage.

Therefore,

if

the

source

voltage

exceeds

a

certain

limit,

the

output

voltage

and

the

threshold

voltage

will

not

balance,

as

a

result

of

which

operation

will

become

impossible.

With

a

C-MOS,

the

threshold

voltage

varies

according

to

changes

in

the

source

voltage,

and

stable

operation

throughout

a

wide

range

can

be

expected.

As

indicated

above,

the

performance

of

a

C-MOS

IC

as

a

digital

IC

is

excellent.

VoD

P-channel

MOS

FET

Output

N-channel

MOS

FET

o

Fig.

2.1.1

C-MOS

Inverter

a

-#

a

oO

Ny

OUTPUT

VOLTAGE

(V)

4

2

3

4

5

6

INPUT

VOLTAGE(V)

°

Fig.

2.1.2

Input-Output

Transmission

Characteristics

<

=

Oo

oO

OUTPUT

VOLTAGE

(V)

oO

ie)

5

10

415

INPUT

VOLTAGE

(V)

Fig.

2.1.3

Input-Output

Transfer

Characteristics

of

C-MOS

(The

threshold

voltage

is

approxi-

mately

half

of

VDD.)

(2)

Gate

Logic

2-input

NAND

gate

is

used.

Following

show

each

of

logic

symbol,

truth

table,

assignment,

and

internal

schematic

diagram.

The

output

will

be

L

only

if

inputs

IN1

and

IN2

are

H’s,

and

the

output

will

be

H

if

IN1

is

L

or

IN2

is

L.

Out

IN2

Out

=

INT-IN2-

IN

1

IN

2

ia

Out

=

INT

+

IND

ng

_

Out

=

INT-IN2

=

INT

+

IN2

Fig.

2.1.4

Truth

Table

1

The

construction

of

the

foregoing

2

Logic

Symbols

is

identical

and

intended

to

show

the

use

of

either

AND

or

OR.

(3)

Gated

Filp-Flop

The

two

NAND

gates

can

be

used

to

form

flip-flop.

The

inputs

operate

as

follows:

When

both

S

and

R

are

H’s,

the

flip-flop

will

remain

in

its

present

state,

i.e.,

will

not

change

the

state.

If

however,

the

R

input

goes

to

L,

the

NAND

gate

connected

to

R

will

have

H

output

regardless

of

the

other

feedback

input

to

the

NAND

gate,

and

this

will

force

the

flip-flop

to

the

L

state

{provided

the

S

input

is

kept

H).

Similar

reasoning

shows

that

making

the

S

input

an

L

will

cause

the

NAND

gate

at

the

S

input

to

have

an

H

output,

forcing

the

flip-flop

to

the

H

state

(again

provided

the

R

input

is

kept

H).

If

both

inputs

R

and

S

are

made

L’s,

the

will

depend

on

which

input

is

returned

to

H

first,

and

if

both

are

returned

to

H

simultaneously,

the

resulting

state

of

the

filp-flop

will

be

indeterminate.

As

a

result,

this

is

a

“forbidden”

or

“restricted”

input

combination.

(4)

Compatible

C-MOS

ICs

1C306:

ywPD4011C,

CD4011A,

MC14011A,

F34011A,

TP4011A,

TC4011P

Vop

A4

B4

Y4

Y3

A3

B3

Ai

B1

Set

(s)

Reset

(Rr)

Yi

Y2

Az

B2

GND

(TOP

VIEW)

Fig.

2.1.5

VoD

GND

Fig.

2.1.6

Q

Fig.

2.1.7

Truth

Table

2

*:

Maintains

the

2.1.2.

Operational

Amplifier

IC

Most

operational

amplifier

IC‘s

consist

of

a

differential

amplifier

with

a

voltage

amplification

of

70

to

100

dB.

High-gain

amplifier

circuits,

oscillators

or

comparators

use

operational

amplifier

IC.

(Vin

—

Vin

(—))

x

Av

=

Vout

Vin

Vout

Vin(-)

Gain=Av

Fig.

2.1.8

Operational

Amplifier

(1)

Voltage

follower

circuit

This

circuit

is

a

special-purpose

non-inverting

amplifier.

It

is

used

for

converting

impedance

when

the

impedance

of

the

input

signal

source

is

too

high

and

the

input

impedance

of

the

following

step

is

too

low

for

direct

connection.

The

special

feature

of

the

voltage

follower

is

high

input

impedance

and low

output

impedance.

Its

voltage

gain

is

1.

(Vin

—

Vout)

x

Av

=

Vout

_

a,

Au

+

Vout

=

Vout

(1

+)

=

Vout

Vin

=

Vout

Fig.

2.1.9

Voltage

Follower

Circuit

(2)

Amplifier

circuit

Two

types

of

amplifier

circuits

are

the

inverting

amplifier

and

the

non-inverting

amplifer.

The

amplification

factor

R,

+

Ro

Ra

:

Inverting

circuits

output

signals

of

phases

opposite

to

those

of

the

input

signals.

of

these

circuits

is

:

R2

=

(Vin

—

Vout

Ri

+

R,)

x

Av

=

Vout

:

Vout

R,

=————

+

—_—

Vin

Ay

Vout

R,

+R,

1

R,

=

V

—._

++

+

ue

tA

R;

+

R2

Es

Re

by

ab

os

=

Vout

Ry

Re

Ge

Ay

=

0)

Vout

=

Vin

Ri

+

Ro

Vout

Fig.

2.1.10

Non-inverting

Fig.

2.1.11

Inverting

(3)

Oscillator

(Astable

Multivibrator)

The

operational

amplifier amplifies

the

difference

be-

tween

non-inverting

input

and

inverting

input,

and

gen-

erally

its

output

is

amplified

up

to

the

source

voltage

because

of

the

high

voltage

amplification.

in

the

circuit

shown

in

Fig.

2.1.12.,

Vout

equals

the

positive

source

voltage

when

the

non-inverting

input

is

larger

than

the

inverting

input.

The

voltage

of

the

non-inverting

input

is

R

of

the

positive

source

2

+

R3

voltage.

On

the

other

hand,

because

C1

is

charged

by

the

Vout

voltage

through

R1,

the

inverting

input

rises

to

the

positive

source

voltage.

However,

when

it

exceeds

the

voltage

of

the

non-inverting

input,

Vout

is

inverted

to

the

negative

source

voltage.

The

voltage

of

the

non-inverting

sal

ae

of

the

negative

source

voltage.

When

C,

is

discharged

through

R;

and

the

voltage

of

the

inverting

input

becomes

lower

than

that

of

the

non-

inverting

input,

Vout

is

again

inverted

to

the

positive

source

voltage.

By

repeating

these

operations,

the

circuit

acts

as

an

astable

multivibrator.

See

Fig.

2.1.13

timing

chart.

input

then

is

2R2

T

=

2C;

Ri

2n(1

+

)

[sec.]

R3

Fig.

2.1.12

Oscillator

R2

Inverting

R2+R3

Input

R

2

—VRZ+RS

R2

+Va55RF

Non

-Inverting

R2+R3

Input

R2

—VR2+R3

+V

V

out

—V

Fig.

2.1.13

Timing

Chart

(4)

Peak

holding

circuit

;

Figs.

2.1.14.

and

2.1.15.

show

the

peak

holding

circuit

for

Input

Output

positive

input

voltage

and

its

timing

chart.

This

circuit

holds

the

peak

value

of

the

input

voltage.

R]c

When

the

input

signals

are

pulses,

the

capacitor

C

ng

repeatedly

charges

and

dischages

to

hold

the

peak

value.

:

When

no

pulse

is

supplied,

C

is

discharged

through

R

and

Fig.

2.1.14

Peak

Holding

Circuit

the

output

becomes

O

with

a

certain

time

constant.

It

is

used

in

the

N-530

in

combination

with

an

oscillator

for

frequency-voltage

conversion.

A

J

Tc

{Input

t

E-e

CR

Output

E

Fig.

2.1.15

Timing

Chart

2.1.3.

Quadrature

Detector

is

supplied

to

another.

The

pulse

width

of

output

iL

varies

Figs.

2.1.16.-2.1.18.

show

the

structure

and

operation

according

to

the

phase

difference

between

the

direct

input

principle

of

the

quadrature

detector.

It

is

a

phase

detector

e,

and

the

input

through

the

phase

shifter

e2

and

phase

in

which

a

direct

signal

is

supplied

to

an

input

terminal

of

detection

is

made

by

the

increase

and

decrease

of

the

multiplier,

and

a

signal

through

a

90°

phase

shifter

mean

value

iav.

90°t

AD

Multiplier

P

Phase

(chadearere)

me

eal

©

Output

Shifter

Detector

Go

Audio

Preamp,

Input

Limiting

Amp,

Cin

Fig.

2.1.16

Quadrature

Detector

System

Diagram

I

Shifter

.

90°t

40

it

{

i2

€2

0

i

average

Fig.

2.1.17

Quadrature

Detector

Circuit

i

|

Fig.

2.1.18

Timing

Chart

2.2.

Power

Mute

Signal

-

Refer

to

the

timing

chart

in

Fig.

2.2.1.

and

circuit

diagram

in

Fig.

2.2.2.

(1)

Power

ON

When

the

Power

Switch

is

pressed

to

power

ON,

+12V,

+40V

and

+18V

Power

Source

will

be

supplied.

In

the

meantime,

when

Q306

is

turned

OFF,

C309

(33

uF

25

V)

will

be

charged

via

R314

(1

MQ),

then

0307

will

be

turned

ON

approx.

2

seconds

later

to

release

the

Power

Mute

Signal.

In

other

words

the

said

Power

Mute

Signal

will

bring

the

N-530

in

Mute

condition

approx.

2

seconds

after

the

Power

Switch

is

pressed

ON.

Power

Mute

=

L

will

enter

the

Preout

Mute

Circuit

(0107

and

0207)

and

Auto

Tuning

flip-flops

of

the

Main

P.C.B.,

and

mutes

each

output

terminal

and

resets

each

flip-flop.

It

is

also

supplied

to

the

Relay

RL301

to

turn

OFF

and

opens

the

supply

to

Speaker

System.

When

Power

Mute

Signal

is

released,

the

Relay

RL301

becomes

turned

ON

and

Speaker

System

will

be

con-

nected,

(2)

Power

OFF

When

the

Power

Switch

is

released

to

power

OFF,

+12V,

+40V

and

+18V

will

no

longer

be

supplied,

Q306

is

turned

ON

during

discharge

of

C308

(47

uF

25

V)

via

0304

and

R313

(2.2

MQ).

When

O306

is

turned

ON,

C309

will

immediately

be

discharged

via

Q306.

This

way

Q307

and

Q308

will

be

turned

OFF,

Power

Mute

=

L

will

be

supplied

to

the

Main

P.C.B.

1C304

pA7B42M

D302

Q304

2SA733

R306

3.3K

R308

400K

fe)

C307

2200

25v

R307

40K

R309

400K

DC

Voltage

Detector

Abnormal

Temperature

Detector

Power

Switch

+42V

t4ov

48V

Q304

Q306

C309

Q307

Q308

Power

Mute

Q306

280945

ON

OFF

ON

OFF

ON

OFF

ON

OFF

OV

ON

OFF

H

L

Fig.

R314

4M

C309

33y

25V(LN)

2.2.1

Power

Mute

Timing

Chart

Q307

28$€1400

2SA750

(4)

©

Power

Mute

R347

40K

—18V

Fig.

2.2.2

Power

Mute

Generating

Circuit

2.3.

Tuner

Section

2.3.1.

FM

MPX

Stereo

Broadcasting

Operation

As

is

generally

known,

the

amplitude

of

the

carrier

wave

is

modulated

in

AM

broadcasting

whereas

the

carrier

fre-

quency

is

modulated

in

FM

broadcasting.

Fig.

2.3.1.

illustrates

these

conditions.

FM

transmitters

and

receivers,

although

considerably

more

complicated

than

those

for

AM

broadcasting,

permit

radio

reception

with

very

high

fidelity

and

any

difference

in

technical

skill

will

be

noticeably

manifested

in

the

performance

of

the

equipment.

Compared

to

AM

broad-

casting,

FM

broadcasting

has

many

advantages,

such

as

better

frequency

response,

higher

S/N

ratio,

less

inter-

ference,

less

distortion,

etc.

However,

its

greatest

advan-

tage

is

the

capability

for

compatible

stereo

broadcasting.

This

is

achieved

by

employing

a

composite

signal,

as

shown

in

“4”

of

Fig.

2.3.2.

instead

of

the

audio

signal

shown

in

Fig.

2.3.1.

Since

the

composite

signals

transmitted

in

ordinary

broadcasting

have

an

extremely

complex

waveform,

it

is

hard

to

recognize

them,

even

when

observed

with

an

oscilloscope.

Figure

2.3.2.

illustrates

an

L

channel

signal

of

1900

Hz

with

no

R

channel

signal.

As

shown

in

“1”

of

Fig.

2.3.2.,

this

is

a

stereo

signal

modulated

so

as

to

swing

at

38

kHz

between

the

L

channel

signal

and

R

channel

signal.

Therefore,

this

signal

can

be

separated

into

L

ch/R

ch,

by

a

synchronizing

signal

with

the

38

kHz

of

the

stereo

signal

and

a

circuit

which

is

conducting

at

the

positive

peak

and

negative

peak

of

this

synchronizing

signals;

the

L

ch/R

ch

signals

will

come

out

separately.

But,

as

is

shown

by

the

signal

waveform

“1”

in

Fig.

2.3.2.,

since

the

phase

at

38

kHz

is

reversed

between

the

positive

and

negative

half-cycles

of

the

L

ch

signal,

even

with

the

separation

described

above,

it

is

not

possible

to

distinguish

L

ch

from

R

ch.

Audio

Signal

Carrier

Noise

mixes

Under

these

conditions,

it is

possible

that

the

L

ch/R

ch

is

reversed

each

time

the

power

switch

is

turned

ON/OFF,

Here

lies

the

importance

of

the

pilot

signal.

That

is,

when

making

the

38

kHz

signal

(’’3”

in

Fig.

2.3.2)

by

doubling

the

19

kHz

pilot

signal,

if

the

positive

and

negative

peaks

of

the

19

kHz

wave

are

synchronized

with

a

negative

peak

at

the

38

kHz,

L

channel

can

be

taken

out

at

the

positive

peak

of

the

38

kHz

signal

and

the

R

channel!

at

the

L-Signal

Envelope

R~Signal

Envelope

Stereo

Signal

Modulated

at

38

kHz

L-Signal

1900Hz

R-Signal

O

Ole

rial

|

CRU

OU

h

Ua

CAC

VAC

AUAY

19

kHz

@

38

kHz

®

Composite

Signal

Fig.

2.3.2

MPX

Stereo

Signal

demodulated

Limiter

unusable

>

Cut

by

limiter

aa

ave

rac

ae

Fig.

2.3.1

AM

and

FM

Nakamichi 530 Manuel utilisateur

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