Maxim DS33Z41 Manuel utilisateur

1 of 167 REV: 122006

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

GENERAL DESCRIPTION

The DS33Z41 extends a 10/100 Ethernet LAN

segment by encapsulating MAC frames in HDLC or

X.86 (LAPS) for transmission over up to four

interleaved PDH/TDM data streams using robust,

balanced, and programmable inverse multiplexing.

The Interleave Bus (IBO) serial link supports

seamless bidirectional interconnection with Dallas

Semiconductor’s T1/E1 framers and transceivers.

The device performs store-and-forward of packets

with full wire-speed transport capability. The built-in

Committed Information Rate (CIR) Controller

provides fractional bandwidth allocation up to the

line rate in increments of 512kbps.

FUNCTIONAL DIAGRAM

FEATURES

 10/100 IEEE 802.3 Ethernet MAC (MII and

RMII) Half/Full Duplex with Automatic Flow

Control

 Layer 1 Inverse Multiplexing Allows Bonding of

Up to 4 T1/E1/J1 or DSL Links

 Supports Up to 7.75ms Differential Delay

 Channel (Byte) Interleaved Bus Operation

 In-Band OAM and Signaling Capability

 HDLC/LAPS Encapsulation with Programmable

FCS, Interframe Fill

 Committed Information Rate Controller Provides

Fractional Allocation in 512kbps Increments

 Programmable BERT for the Serial Interface

 External 16MB, 100MHz SDRAM Buffering

 Parallel Microprocessor Interface

 1.8V Operation with 3.3V Tolerant I/O

 IEEE 1149.1 JTAG Support

Features continued on page 8.

APPLICATIONS

Bonded Transparent LAN Service

LAN Extension

Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1,

G.SHDSL, or HDSL2/4

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS33Z41 -40°C to +85°C 169 CSBGA

10/100

MAC

SDRAM

MII/RMII

Config.

Loader

DS33Z41

10/100

Ethernet

PHY

Serial

Port

Up to 4

Transceivers

or Framers

BERT

HDLC/X.86

Mapper

IBO

DS33Z41

Quad IMUX Ethernet Mapper

www.maxim-ic.com

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TABLE OF CONTENTS

1DESCRIPTION....................................................................................................................7

2FEATURE HIGHLIGHTS ....................................................................................................8

2.1 GENERAL ......................................................................................................................................8

2.2 LINK AGGREGATION (INVERSE MULTIPLEXING) ...............................................................................8

2.3 HDLC ...........................................................................................................................................8

2.4 COMMITTED INFORMATION RATE (CIR) CONTROLLER.....................................................................8

2.5 X.86 SUPPORT..............................................................................................................................8

2.6 SDRAM INTERFACE ......................................................................................................................9

2.7 MAC INTERFACE ...........................................................................................................................9

2.8 MICROPROCESSOR INTERFACE ......................................................................................................9

2.9 TEST AND DIAGNOSTICS ................................................................................................................9

2.10 SPECIFICATIONS COMPLIANCE .....................................................................................................10

3APPLICATIONS................................................................................................................11

4ACRONYMS AND GLOSSARY........................................................................................12

5MAJOR OPERATING MODES .........................................................................................13

6BLOCK DIAGRAMS .........................................................................................................13

7PIN DESCRIPTIONS.........................................................................................................14

7.1 PIN FUNCTIONAL DESCRIPTION ....................................................................................................14

8FUNCTIONAL DESCRIPTION..........................................................................................22

8.1 PROCESSOR INTERFACE ..............................................................................................................23

8.1.1 Read-Write/Data Strobe Modes..........................................................................................................23

8.1.2 Clear on Read.....................................................................................................................................23

8.1.3 Interrupt and Pin Modes......................................................................................................................23

8.2 CLOCK STRUCTURE..................................................................................................................... 24

8.2.1 Serial Interface Clock Modes..............................................................................................................26

8.2.2 Ethernet Interface Clock Modes .........................................................................................................26

8.3 RESETS AND LOW-POWER MODES...............................................................................................27

8.4 INITIALIZATION AND CONFIGURATION ............................................................................................28

8.5 GLOBAL RESOURCES...................................................................................................................28

8.6 PER-PORT RESOURCES............................................................................................................... 28

8.7 DEVICE INTERRUPTS....................................................................................................................29

8.8 SERIAL INTERFACE ......................................................................................................................31

8.9 LINK AGGREGATION (IMUX).........................................................................................................31

8.9.1 Microprocessor Requirements............................................................................................................33

8.9.2 IMUX Command Protocol ...................................................................................................................34

8.9.3 Out of Frame (OOF) Monitoring..........................................................................................................36

8.9.4 Data Transfer ......................................................................................................................................36

8.10 CONNECTIONS AND QUEUES........................................................................................................37

8.11 ARBITER .....................................................................................................................................38

8.12 FLOW CONTROL ..........................................................................................................................39

8.12.1 Full-Duplex Flow Control.....................................................................................................................40

8.12.2 Half-Duplex Flow control.....................................................................................................................41

8.12.3 Host-Managed Flow control ................................................................................................................41

8.13 ETHERNET INTERFACE PORT .......................................................................................................42

8.13.1 DTE and DCE Mode ...........................................................................................................................43

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8.14 ETHERNET MAC.......................................................................................................................... 46

8.14.1 MII Mode .............................................................................................................................................47

8.14.2 RMII Mode ..........................................................................................................................................47

8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................48

8.15 BERT .........................................................................................................................................48

8.15.1 BERT Features ...................................................................................................................................48

8.15.2 Receive Data Interface .......................................................................................................................49

8.15.3 Repetitive Pattern Synchronization.....................................................................................................49

8.15.4 Pattern Monitoring...............................................................................................................................50

8.15.5 Pattern Generation..............................................................................................................................50

8.16 TRANSMIT PACKET PROCESSOR ..................................................................................................52

8.17 RECEIVE PACKET PROCESSOR ....................................................................................................53

8.18 X.86 ENCODING AND DECODING..................................................................................................55

8.19 COMMITTED INFORMATION RATE CONTROLLER ............................................................................58

9DEVICE REGISTERS .......................................................................................................60

9.1 REGISTER BIT MAPS....................................................................................................................61

9.1.1 Global Register Bit Map ......................................................................................................................61

9.1.2 Arbiter Register Bit Map......................................................................................................................62

9.1.3 BERT Register Bit Map.......................................................................................................................62

9.1.4 Serial Interface Register Bit Map ........................................................................................................63

9.1.5 Ethernet Interface Register Bit Map....................................................................................................65

9.1.6 MAC Register Bit Map ........................................................................................................................66

9.2 GLOBAL REGISTER DEFINITIONS ..................................................................................................68

9.3 ARBITER REGISTERS ...................................................................................................................81

9.3.1 Arbiter Register Bit Descriptions.........................................................................................................81

9.4 BERT REGISTERS.......................................................................................................................82

9.5 SERIAL INTERFACE REGISTERS ....................................................................................................89

9.5.1 Serial Interface Transmit and Common Registers..............................................................................89

9.5.2 Serial Interface Transmit Register Bit Descriptions ............................................................................89

9.5.3 Transmit HDLC Processor Registers..................................................................................................90

9.5.4 X.86 Registers ....................................................................................................................................97

9.5.5 Receive Serial Interface......................................................................................................................99

9.6 ETHERNET INTERFACE REGISTERS.............................................................................................112

9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................112

9.6.2 MAC Registers..................................................................................................................................124

10 FUNCTIONAL TIMING....................................................................................................140

10.1 MII AND RMII INTERFACES ........................................................................................................140

11 OPERATING PARAMETERS .........................................................................................142

11.1 THERMAL CHARACTERISTICS .....................................................................................................143

11.2 MII INTERFACE..........................................................................................................................144

11.3 RMII INTERFACE .......................................................................................................................146

11.4 MDIO INTERFACE .....................................................................................................................148

11.5 TRANSMIT WAN INTERFACE ......................................................................................................149

11.6 RECEIVE WAN INTERFACE ........................................................................................................150

11.7 SDRAM TIMING ........................................................................................................................151

11.8 MICROPROCESSOR BUS AC CHARACTERISTICS .........................................................................155

11.9 JTAG INTERFACE TIMING ..........................................................................................................158

12 JTAG INFORMATION.....................................................................................................159

12.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION...........................................................160

12.2 INSTRUCTION REGISTER ............................................................................................................162

12.2.1 SAMPLE:PRELOAD .........................................................................................................................163

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12.2.2 BYPASS............................................................................................................................................163

12.2.3 EXTEST ............................................................................................................................................163

12.2.4 CLAMP..............................................................................................................................................163

12.2.5 HIGHZ...............................................................................................................................................163

12.2.6 IDCODE ............................................................................................................................................163

12.3 JTAG ID CODES .......................................................................................................................164

12.4 TEST REGISTERS ......................................................................................................................164

12.4.1 Boundary Scan Register ...................................................................................................................164

12.4.2 Bypass Register................................................................................................................................164

12.4.3 Identification Register .......................................................................................................................164

12.5 JTAG FUNCTIONAL TIMING........................................................................................................165

13 PACKAGE INFORMATION ............................................................................................166

13.1 169-BALL CSBGA, 14MM X 14MM (56-G6035-001)...................................................................166

14 DOCUMENT REVISION HISTORY.................................................................................167

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LIST OF FIGURES

Figure 3-1. Quad T1/E1 SCT to DS33Z41 .............................................................................................................. 11

Figure 6-1. Detailed Block Diagram......................................................................................................................... 13

Figure 7-1. DS33Z41 256-Ball CSBGA Pinout........................................................................................................ 21

Figure 8-1. Clocking for the DS33Z41..................................................................................................................... 25

Figure 8-2. Device Interrupt Information Flow Diagram .......................................................................................... 30

Figure 8-3. IMUX Interface to T1/E1 Transceivers.................................................................................................. 32

Figure 8-4. Diagram of Data Transmission with IMUX Operation ........................................................................... 32

Figure 8-5. Command Structure for IMUX Function................................................................................................ 34

Figure 8-6. Flow Control Using Pause Control Frame ............................................................................................ 41

Figure 8-7. IEEE 802.3 Ethernet Frame.................................................................................................................. 42

Figure 8-8. Configured as DTE Connected to an Ethernet PHY in MII Mode......................................................... 44

Figure 8-9. DS33Z41 Configured as a DCE in MII Mode ........................................................................................ 45

Figure 8-10. RMII Interface...................................................................................................................................... 47

Figure 8-11. MII Management Frame...................................................................................................................... 48

Figure 8-12. PRBS Synchronization State Diagram................................................................................................ 49

Figure 8-13. Repetitive Pattern Synchronization State Diagram............................................................................. 50

Figure 8-14. LAPS Encoding of MAC Frames Concept .......................................................................................... 55

Figure 8-15. X.86 Encapsulation of the MAC field .................................................................................................. 56

Figure 8-16. CIR in the WAN Transmit Path ........................................................................................................... 59

Figure 10-1. MII Transmit Functional Timing......................................................................................................... 140

Figure 10-2. MII Transmit Half Duplex with a Collision Functional Timing............................................................ 140

Figure 10-3. MII Receive Functional Timing.......................................................................................................... 141

Figure 10-4. RMII Transmit Interface Functional Timing ....................................................................................... 141

Figure 10-5 RMII Receive Interface Functional Timing ......................................................................................... 141

Figure 11-1. Transmit MII Interface ....................................................................................................................... 144

Figure 11-2. Receive MII Interface Timing ............................................................................................................ 145

Figure 11-3. Transmit RMII Interface..................................................................................................................... 146

Figure 11-4. Receive RMII Interface Timing.......................................................................................................... 147

Figure 11-5. MDIO Timing ..................................................................................................................................... 148

Figure 11-6. Transmit WAN Timing ....................................................................................................................... 149

Figure 11-7. Receive WAN Timing ........................................................................................................................ 150

Figure 11-8. SDRAM Interface Timing .................................................................................................................. 152

Figure 11-9. Receive IBO Channel Interleave Mode Timing................................................................................. 153

Figure 11-10. Transmit IBO Channel Interleave Mode Timing.............................................................................. 154

Figure 11-11. Intel Bus Read Timing (MODEC = 00)............................................................................................ 156

Figure 11-12. Intel Bus Write Timing (MODEC = 00) ............................................................................................ 156

Figure 11-13. Motorola Bus Read Timing (MODEC = 01) .................................................................................... 157

Figure 11-14. Motorola Bus Write Timing (MODEC = 01)..................................................................................... 157

Figure 11-15. JTAG Interface Timing Diagram ..................................................................................................... 158

Figure 12-1. JTAG Functional Block Diagram....................................................................................................... 159

Figure 12-2. TAP Controller State Diagram .......................................................................................................... 162

Figure 12-3. JTAG Functional Timing.................................................................................................................... 165

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LIST OF TABLES

Table 2-1. T1 Related Telecommunications Specifications .................................................................................... 10

Table 7-1. Detailed Pin Descriptions ....................................................................................................................... 14

Table 8-1. Clock Selection for the Ethernet (LAN) Interface ................................................................................... 24

Table 8-2. Reset Functions ..................................................................................................................................... 27

Table 8-3. Commands Sent and Received on the IMUX Links............................................................................... 34

Table 8-4. Command and Status for the IMUX for Processor Communication....................................................... 35

Table 8-5. Registers Related to Connections and Queues ..................................................................................... 38

Table 8-6. Options for Flow Control......................................................................................................................... 39

Table 8-7. Registers Related to the Ethernet Port .................................................................................................. 43

Table 8-8. MAC Control Registers........................................................................................................................... 46

Table 8-9. MAC Status Registers ............................................................................................................................ 46

Table 9-1. Register Address Map............................................................................................................................ 60

Table 9-2. Global Register Bit Map ......................................................................................................................... 61

Table 9-3. Arbiter Register Bit Map ......................................................................................................................... 62

Table 9-4. BERT Register Bit Map .......................................................................................................................... 62

Table 9-5. Serial Interface Register Bit Map ........................................................................................................... 63

Table 9-6. Ethernet Interface Register Bit Map ....................................................................................................... 65

Table 9-7. MAC Indirect Register Bit Map............................................................................................................... 66

Table 11-1. Recommended DC Operating Conditions.......................................................................................... 142

Table 11-2. DC Electrical Characteristics.............................................................................................................. 142

Table 11-3. Thermal Characteristics ..................................................................................................................... 143

Table 11-4. Theta-JA vs. Airflow ........................................................................................................................... 143

Table 11-5. Transmit MII Interface ........................................................................................................................ 144

Table 11-6. Receive MII Interface ......................................................................................................................... 145

Table 11-7. Transmit RMII Interface...................................................................................................................... 146

Table 11-8. Receive RMII Interface....................................................................................................................... 147

Table 11-9. MDIO Interface ................................................................................................................................... 148

Table 11-10. Transmit WAN Interface ................................................................................................................... 149

Table 11-11. Receive WAN Interface.................................................................................................................... 150

Table 11-12. SDRAM Interface Timing.................................................................................................................. 151

Table 11-13. AC Characteristics—Microprocessor Bus Timing ............................................................................ 155

Table 11-14. JTAG Interface Timing ..................................................................................................................... 158

Table 12-1. Instruction Codes for IEEE 1149.1 Architecture ................................................................................ 163

Table 12-2. ID Code Structure............................................................................................................................... 164

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1 DESCRIPTION

The DS33Z41 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN

Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a

10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller (CIR), HDLC/X.86 (LAPS) Mapper,

SDRAM interface, control ports, and Bit Error Rate Tester (BERT). The packet interface consists of an Ethernet

interface using several physical layer protocols. The Ethernet interface can be configured for 10Mbps or 100Mbps

service. The DS33Z41 encapsulates Ethernet traffic with HDLC or X.86 (LAPS) to be transmitted over the WAN

interface. The WAN interface also receives encapsulated Ethernet packets and transmits the extracted packets

over the Ethernet port. The WAN physical interface is based on the Dallas Semiconductor Interleaved Bus

Operation (IBO), running at 8.192Mbps. The IBO interface can be configured to allow up to four bonded T1 or E1

data streams. The IBO interface provides for seamless connection to the Dallas Semiconductor/Maxim multi-port

T1/E1/J1 Framers and Single-Chip Transceivers (SCTs). See Application Note 3411: DS33Z11—Ethernet LAN to

Unframed T1/E1 WAN Bridge for an example of a complete LAN to WAN solution.

The DS33Z41 is controlled through an 8-bit microcontroller port. The DS33Z41 has a 100MHz SDRAM controller

and interfaces to a 32-bit wide 128Mb SDRAM. The SDRAM is used to buffer the data from the Ethernet and

WAN ports for transport. The external SDRAM can accommodate up to 8192 frames with a maximum frame size

of 2016 bytes. The DS33Z41 operates with a 1.8V core supply and 3.3V I/O supply.

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2 FEATURE HIGHLIGHTS

2.1 General

• 169-pin, 14mm x 14mm CSBGA package

• 1.8V supply with 3.3V tolerant inputs and outputs

• IEEE 1149.1 JTAG boundary scan

• Software access to device ID and silicon revision

• Development support includes evaluation kit, driver source code, and reference designs

2.2 Link Aggregation (Inverse Multiplexing)

• Link aggregation for up to 4 T1/E1 Links

• 8.192Mbps IBO interface to Dallas Semiconductor Framers/Transceivers

• Differential delay compensation up to 7.75ms for the 4 T1/E1 links

• Handshaking protocol between local and distant end for establishment of aggregation

2.3 HDLC

• HDLC controller engine

• Compatible with polled or interrupt driven environments

• Programmable FCS insertion and extraction

• Programmable FCS type

• Supports FCS error insertion

• Programmable packet size limits (Minimum 64 bytes and maximum 2016 bytes)

• Supports bit stuffing/destuffing

• Selectable packet scrambling/descrambling (X43+1)

• Separate FCS errored packet and aborted packet counts

• Programmable inter-frame fill for transmit HDLC

2.4 Committed Information Rate (CIR) Controller

• CIR controller limits transmission of data from the Ethernet Interface to the Serial Interface.

• CIR granularity at 512kbps

• CIR Averaging for smoothing traffic peaks

2.5 X.86 Support

• Programmable X.86 address/control fields for transmit and receive

• Programmable 2-byte protocol (SAPI) field for transmit and receive

• 32 bit FCS

• Transmit Transparency processing - 7E is replaced by 7D, 5E

• Transmit Transparency processing – 7D replaced by 7D, 5D

• Receive rate adaptation (7D, DD) is deleted.

• Receive Transparency processing - 7D, 5E is replaced by 7E

• Receive Transparency processing – 7D, 5D is replaced by 7D

• Receive Abort Sequence the LAPS packet is dropped if 7D7E is detect

• Self-synchronizing X43+1 payload scrambling.

• Frame indication due to bad Address/Control/SAPI, FCS error, abort sequence or frame size longer

than preset max.

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2.6 SDRAM Interface

• Interface for 128Mb, 32-bit-wide SDRAM

• SDRAM Interface speed up to 100MHz

• Auto Refresh Timing

• Automatic Precharge

• Master clock provided to the SDRAM

• No external components required for SDRAM connectivity

2.7 MAC Interface

• MAC port with standard MII (less TX_ER) or RMII

• 10Mbps and 100Mbps Data rates

• Configurable DTE or DCE modes

• Facilitates auto-negotiation by host microprocessor

• Programmable half and full-duplex modes

• Flow control for both half-duplex (back-pressure) and full-duplex (PAUSE) modes

• Programmable Maximum MAC frame size up to 2016 bytes

• Minimum MAC frame size: 64 bytes

• Discards frames greater than Programmed Maximum MAC frame size and Runt, non-octet bounded,

or bad-FCS frames upon reception

• Programmable threshold for SDRAM queues to initiate flow control and status indication

• MAC Loopback support for Transmit data looped to Receive Data at the MII/RMII interface

2.8 Microprocessor Interface

• 8 bit data bus

• Non-multiplexed Intel and Motorola Timing Modes

• Internal software reset and External Hardware reset input pin

• Global interrupt output pin

2.9 Test and Diagnostics

• IEEE 1149.1 Support

• Programmable on-chip Bit Error Rate Tester (BERT)

• Patterns include Pseudorandom QRSS, Daly, and user-defined repetitive patterns

• Loopbacks (remote, local, analog, and per-channel loopback)

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2.10 Specifications compliance

The DS33Z41 meets relevant telecommunications specifications. The following table provides the specifications

and relevant sections that are applicable to the DS33Z41.

Table 2-1. T1 Related Telecommunications Specifications

IEEE 802.3-2002—CSMA/CD access method and physical layer specifications

RFC1662—PPP in HDLC-like Framing

RFC2615—PPP over SONET/SDH

X.86—Ethernet over LAPS

RMII—Industry Implementation Agreement for “Reduced MII Interface” (Sept. 1997)

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