CPU DATA BUS
The CPU utilizes an 8-bit bidirectional data bus.
The data bus is used for data exchanges with memory and I/O
devices. The data is buffered through U4 and U17. DBIN
(Ul-10) is used for directional control. When DBIN is a
logic "1" the CPU is receiving data. When DBIN is low the
CPU is sending data.
WAIT*, INT*, and TEST*
The WAIT* input to the Z80A CPU will cause the Z80A
to extend its cycle, resulting in slowing down the CPU. The
LNW80 utilizes one WAIT function when aROM read is in
process and one or two waits when accessing the video
memory. These waits are required in the hi-speed mode of
4MHz to ensure data validity when accessing the slower
memory devices. There are no wait states when accessing the
program memory (RAM) on the LNW80 (requiring 200ns or faster
RAM 's)
.
The wait term is generated by U31. U31-3, the
clock, is delayed by U16. This clock delay results in
proper data setup time to U31. U61-3 is WAITHLD. This will
increase the wait from the usual one wait state for the
Level II ROM's, to multiple wait states when reading from
the video memory. Pin 33 of Jl is the bus WAIT signal.
This input may be utilized by other external devices that
may wish to pose await condition on the Z80A procesor.
The INT* signal is amaskable interrupt to the Z80A
pin 16. The Level II Basic ROM utilizes interrupt mode 1.
When the CPU is interrupted, arestart to location 0038H is
executed.
Pin 23 of Jl is TEST* which is abusrequest signal
to the Z80A CPU. The CPU responds by tri-stating its data,
address and output control signals. Since the Z80A CPU is
fully buffered, all the buffers (U3, U4, U5, U17, and U18)
will also be tri-stated. Once these buffers are tri-stated,
any device on the expansion bus may control the function of
the LNW80 board. One important consideration is that the
dynamic program RAM's are refreshed by the Z80A processor.
Therefore, any controlling device on the expansion bus must
consider memory refresh.
