Linear Technology LTC6804-1 Manuel utilisateur

LTC6804-1/LTC6804-2

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Typical applicaTion

FeaTures DescripTion

Multicell Battery Monitors

The LTC

6804 is a 3rd generation multicell battery stack

monitor that measures up to 12 series connected battery

cellswithatotalmeasurementerroroflessthan1.2mV.The

cell measurement range of 0V to 5V makes the LTC6804

suitable for most battery chemistries. All 12 cell voltages

can be captured in 290µs, and lower data acquisition rates

can be selected for high noise reduction.

Multiple LTC6804 devices can be connected in series,

permittingsimultaneouscellmonitoringoflong, highvolt-

age battery strings. Each LTC6804 has an isoSPI interface

for high speed, RF-immune, local area communications.

Using the LTC6804-1, multiple devices are connected in

a daisy-chain with one host processor connection for all

devices. Using the LTC6804-2, multiple devices are con-

nected in parallel to the host processor, with each device

individually addressed.

Additionalfeaturesincludepassivebalancingfor each cell,

an onboard 5V regulator, and 5 general purpose I/O lines.

In sleep mode, current consumption is reduced to 4µA.

The LTC6804 can be powered directly from the battery,

or from an isolated supply.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered and isoSPI is a

trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. patents, including 8908799, 9182428, 9270133.

Total Measurement Error

vs Temperature of 5 Typical Units

applicaTions

n Measures Up to 12 Battery Cells in Series

n Stackable Architecture Supports 100s of Cells

n Built-In isoSPI™ Interface:

1Mbps Isolated Serial Communications

Uses a Single Twisted Pair, Up to 100 Meters

Low EMI Susceptibility and Emissions

n 1.2mV Maximum Total Measurement Error

n 290µs to Measure All Cells in a System

n Synchronized Voltage and Current Measurement

n 16-Bit Delta-Sigma ADC with Frequency Program-

mable 3rd Order Noise Filter

n Engineered for ISO26262 Compliant Systems

n Passive Cell Balancing with Programmable Timer

n 5 General Purpose Digital I/O or Analog Inputs:

Temperature or other Sensor Inputs

Configurable as an I2C or SPI Master

n 4μA Sleep Mode Supply Current

n 48-Lead SSOP Package

n Electric and Hybrid Electric Vehicles

n Backup Battery Systems

n Grid Energy Storage

n High Power Portable Equipment

LTC6820

LTC6804-1

MPU

•

SPI

IPA

IMA

680412 TA01a

IPB

IMB

LTC6804-1

IMA

IPA

ILP

IPB

IMB

LTC6804-1

IMA

IPB

IMB

IPA

12S1P

TEMPERATURE (°C)

–50

MEASUREMENT ERROR (mV)

1.5

680412 TA01b

–1.0

–25 0 50

–1.5

–2.0

2.0

1.0

0.5

–0.5

75 100

125

CELL VOLTAGE = 3.3V

5 TYPICAL UNITS

LTC6804-1/LTC6804-2

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For more information www.linear.com/LTC6804-1

Table oF conTenTs

Features..................................................... 1

Applications ................................................ 1

Typical Application ........................................ 1

Description.................................................. 1

Absolute Maximum Ratings.............................. 3

Pin Configuration .......................................... 3

Order Information.......................................... 4

Electrical Characteristics ................................. 4

Pin Functions .............................................. 17

Block Diagram............................................. 18

Operation................................................... 20

State Diagram.........................................................20

LTC6804 Core State Descriptions...........................20

isoSPI State Descriptions .......................................21

Power Consumption ...............................................21

ADC Operation........................................................21

Data Acquisition System Diagnostics .....................26

Watchdog and Software Discharge Timer ..............30

I2C/SPI Master on LTC6804 Using GPIOS ..............31

Serial Interface Overview........................................35

4-Wire Serial Peripheral Interface (SPI)

Physical Layer ........................................................36

2-Wire Isolated Interface (isoSPI) Physical Layer...36

Data Link Layer.......................................................44

Network Layer ........................................................44

Programming Examples .........................................54

Simple Linear Regulator .........................................58

Improved Regulator Power Efficiency.....................58

Fully Isolated Power................................................59

Reading External Temperature Probes....................59

Expanding the Number of Auxiliary

Measurements........................................................60

Internal Protection Features....................................60

Filtering of Cell and GPIO Inputs.............................60

Cell Balancing with Internal Mosfets.......................62

Cell Balancing with External MOSFETS...................62

Discharge Control During Cell Measurements ........62

Power Dissipation and Thermal Shutdown .............63

Method to Verify Balancing Circuitry ......................63

Current Measurement with a Hall Effect Sensor .....66

Current Measurement with a Shunt Resistor..........66

Using the LTC6804 with Less Than 12 Cells...........67

Package Description ..................................... 76

Revision History .......................................... 77

Typical Application ....................................... 78

Related Parts .............................................. 78

LTC6804-1/LTC6804-2

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absoluTe MaxiMuM raTings

Total Supply Voltage V+to V–....................................75V

Input Voltage (Relative to V–)

C0......................................................... –0.3V to 0.3V

C12 ........................................................ –0.3V to 75V

C(n).....................................–0.3V to MIN (8 •n, 75V)

S(n).....................................–0.3V to MIN (8 •n, 75V)

IPA, IMA, IPB, IMB ....................–0.3V to VREG + 0.3V

DRIVE Pin................................................ –0.3V to 7V

All Other Pins........................................... –0.3V to 6V

Voltage Between Inputs

V+to C12............................................................–5.5V

C(n) to C(n – 1) ........................................ –0.3V to 8V

S(n) to C(n – 1) ........................................ –0.3V to 8V

C12 to C8............................................... –0.3V to 25V

(Note 1)

pin conFiguraTion

C8 to C4................................................. –0.3V to 25V

C4 to C0................................................. –0.3V to 25V

Current In/Out of Pins

All Pins Except VREG, IPA, IMA, IPB, IMB, S(n)..10mA

IPA, IMA, IPB, IMB.............................................30mA

Operating Temperature Range

LTC6804I.............................................–40°C to 85°C

LTC6804H.......................................... –40°C to 125°C

Specified Temperature Range

LTC6804I.............................................–40°C to 85°C

LTC6804H.......................................... –40°C to 125°C

Junction Temperature ........................................... 150°C

Storage Temperature.............................. –65°C to 150°C

Lead Temperature (Soldering, 10sec)....................300°C

LTC6804-1 LTC6804-2

TOP VIEW

G PACKAGE

48-LEAD PLASTIC SSOP

V+

C12

S12

C11

S11

C10

S10

IPB

IMB

ICMP

IBIAS

SDO (NC)*

SDI (NC)*

SCK (IPA)*

CSB (IMA)*

ISOMD

WDT

DRIVE

VREG

SWTEN

VREF1

VREF2

GPIO5

GPIO4

V–

V–**

GPIO3

GPIO2

GPIO1

TJMAX = 150°C, θJA = 55°C/W

*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD

ISOMD TIED TO V–: CSB, SCK, SDI, SDO

ISOMD TIED TO VREG: IMA, IPA, NC, NC

**THIS PIN MUST BE CONNECTED TO V–

TOP VIEW

G PACKAGE

48-LEAD PLASTIC SSOP

V+

C12

S12

C11

S11

C10

S10

SDO (IBIAS)*

SDI (ICMP)*

SCK (IPA)*

CSB (IMA)*

ISOMD

WDT

DRIVE

VREG

SWTEN

VREF1

VREF2

GPIO5

GPIO4

V–

V–**

GPIO3

GPIO2

GPIO1

TJMAX = 150°C, θJA = 55°C/W

*THE FUNCTION OF THESE PINS DEPENDS ON THE CONNECTION OF ISOMD

ISOMD TIED TO V–: CSB, SCK, SDI, SDO

ISOMD TIED TO VREG: IMA, IPA, ICMP, IBIAS

**THIS PIN MUST BE CONNECTED TO V–

LTC6804-1/LTC6804-2

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orDer inForMaTion

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ADC DC Specifications

Measurement Resolution l0.1 mV/bit

ADC Offset Voltage (Note 2) l0.1 mV

ADC Gain Error (Note 2)

0.01

0.02 %

Total Measurement Error (TME) in

Normal Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±0.2 mV

C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV

C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±1.4 mV

C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV

C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±2.2 mV

C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV

C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±2.8 mV

C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±1 mV

Sum of Cells, V(CO) = V–l±0.2 ±0.75 %

Internal Temperature, T = Maximum

Specified Temperature ±5 °C

VREG Pin l±0.1 ±0.25 %

VREF2 Pin l±0.02 ±0.1 %

Digital Supply Voltage VREGD l±0.1 ±1 %

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6804IG-1#PBF LTC6804IG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 85°C

LTC6804HG-1#PBF LTC6804HG-1#TRPBF LTC6804G-1 48-Lead Plastic SSOP –40°C to 125°C

LTC6804IG-2#PBF LTC6804IG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 85°C

LTC6804HG-2#PBF LTC6804HG-2#TRPBF LTC6804G-2 48-Lead Plastic SSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Parts ending with PBF are RoHS and WEEE compliant.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

http://www.linear.com/product/LTC6804-1#orderinfo

LTC6804-1/LTC6804-2

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elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Total Measurement Error (TME) in

Filtered Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±0.1 mV

C(n) to C(n – 1) = 2.0 ±0.1 ±0.8 mV

C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±1.4 mV

C(n) to C(n – 1) = 3.3 ±0.2 ±1.2 mV

C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±2.2 mV

C(n) to C(n – 1) = 4.2 ±0.3 ±1.6 mV

C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±2.8 mV

C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±1 mV

Sum of Cells, V(CO) = V–l±0.2 ±0.75 %

Internal Temperature, T = Maximum

Specified Temperature ±5 °C

VREG Pin l±0.1 ±0.25 %

VREF2 Pin l±0.02 ±0.1 %

Digital Supply Voltage VREGD l±0.1 ±1 %

Total Measurement Error (TME) in

Fast Mode C(n) to C(n – 1), GPIO(n) to V–= 0 ±2 mV

C(n) to C(n – 1), GPIO(n) to V–= 2.0 l±4 mV

C(n) to C(n – 1), GPIO(n) to V–= 3.3 l±4.7 mV

C(n) to C(n – 1), GPIO(n) to V–= 4.2 l±8.3 mV

C(n) to C(n – 1), GPIO(n) to V–= 5.0 ±10 mV

Sum of Cells, V(CO) = V–l±0.3 ±1 %

Internal Temperature, T = Maximum

Specified Temperature ±5 °C

VREG Pin l±0.3 ±1 %

VREF2 Pin l±0.1 ±0.25 %

Digital Supply Voltage VREGD l±0.2 ±2 %

Input Range C(n), n = 1 to 12 lC(n – 1) C(n –1) + 5 V

C0 l0

GPIO(n), n = 1 to 5 l0 5 V

ILInput Leakage Current When Inputs

Are Not Being Measured C(n), n = 0 to 12 l10 ±250 nA

GPIO(n), n = 1 to 5 l10 ±250 nA

Input Current When Inputs Are

Being Measured C(n), n = 0 to 12 ±2 µA

GPIO(n), n = 1 to 5 ±2 µA

Input Current During Open Wire

Detection

l70 100 130 µA

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2

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elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Voltage Reference Specifications

VREF1 1st Reference Voltage VREF1 Pin, No Load l3.1 3.2 3.3 V

1st Reference Voltage TC VREF1 Pin, No Load 3 ppm/°C

1st Reference Voltage Hysteresis VREF1 Pin, No Load 20 ppm

1st Reference Long Term Drift VREF1 Pin, No Load 20 ppm/√kHr

VREF2 2nd Reference Voltage VREF2 Pin, No Load l2.990 3 3.010 V

VREF2 Pin, 5k Load to V–l2.988 3 3.012 V

2nd Reference Voltage TC VREF2 Pin, No Load 10 ppm/°C

2nd Reference Voltage Hysteresis VREF2 Pin, No Load 100 ppm

2nd Reference Long Term Drift VREF2 Pin, No Load 60 ppm/√kHr

General DC Specifications

IVP V+Supply Current

(See Figure 1: LTC6804 Operation

State Diagram)

State: Core = SLEEP

, isoSPI = IDLE VREG = 0V 3.8 6 µA

VREG = 0V l3.8 10 µA

VREG = 5V 1.6 3 µA

VREG = 5V l1.6 5 µA

State: Core = STANDBY 18 32 50 µA

l10 32 60 µA

State: Core = REFUP or MEASURE 0.4 0.55 0.7 mA

l0.375 0.55 0.725 mA

IREG(CORE) VREG Supply Current

(See Figure 1: LTC6804 Operation

State diagram)

State: Core = SLEEP, isoSPI = IDLE VREG = 5V 2.2 4 µA

VREG = 5V l2.2 6 µA

State: Core = STANDBY 10 35 60 µA

l6 35 65 µA

State: Core = REFUP 0.2 0.45 0.7 mA

l0.15 0.45 0.75 mA

State: Core = MEASURE 10.8 11.5 12.2 mA

l10.7 11.5 12.3 mA

IREG(isoSPI) Additional VREG Supply Current if

isoSPI in READY/ACTIVE States

Note: ACTIVE State Current

Assumes tCLK = 1µs, (Note3)

LTC6804-2: ISOMD = 1,

RB1 + RB2 = 2k READY l3.9 4.8 5.8 mA

ACTIVE l5.1 6.1 7.3 mA

LTC6804-1: ISOMD = 0,

RB1 + RB2 = 2k READY l3.7 4.6 5.6 mA

ACTIVE l5.7 6.8 8.1 mA

LTC6804-1: ISOMD = 1,

RB1 + RB2 = 2k READY l6.5 7.8 9.5 mA

ACTIVE l10.2 11.3 13.3 mA

LTC6804-2: ISOMD = 1,

RB1 + RB2 = 20k READY l1.3 2.1 3 mA

ACTIVE l1.6 2.5 3.5 mA

LTC6804-1: ISOMD = 0,

RB1 + RB2 = 20k READY l1.1 1.9 2.8 mA

ACTIVE l1.5 2.3 3.3 mA

LTC6804-1: ISOMD = 1,

RB1 + RB2 = 20k READY l2.1 3.3 4.9 mA

ACTIVE l2.7 4.1 5.8 mA

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2

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elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

V+Supply Voltage TME Specifications Met (Note 6) l11 40 55 V

VREG VREG Supply Voltage TME Supply Rejection < 1mV/V l4.5 5 5.5 V

DRIVE output voltage Sourcing 1µA

5.4

5.2 5.6

5.6 5.8

6.0 V

Sourcing 500µA l5.1 5.6 6.1 V

VREGD Digital Supply Voltage l2.7 3.0 3.6 V

Discharge Switch ON Resistance VCELL = 3.6V l10 25 Ω

Thermal Shutdown Temperature 150 °C

VOL(WDT) Watchdog Timer Pin Low WDT Pin Sinking 4mA l0.4 V

VOL(GPIO) General Purpose I/O Pin Low GPIO Pin Sinking 4mA (Used as Digital Output) l0.4 V

ADC Timing Specifications

tCYCLE

(Figure3) Measurement + Calibration Cycle

Time When Starting from the

REFUP State in Normal Mode

Measure 12 Cells l2120 2335 2480 µs

Measure 2 Cells l365 405 430 µs

Measure 12 Cells and 2 GPIO Inputs l2845 3133 3325 µs

Measurement + Calibration Cycle

Time When Starting from the

REFUP State in Filtered Mode

Measure 12 Cells l183 201.3 213.5 ms

Measure 2 Cells l30.54 33.6 35.64 ms

Measure 12 Cells and 2 GPIO Inputs l244 268.4 284.7 ms

Measurement + Calibration Cycle

Time When Starting from the

REFUP State in Fast Mode

Measure 12 Cells l1010 1113 1185 µs

Measure 2 Cells l180 201 215 µs

Measure 12 Cells and 2 GPIO Inputs l1420 1564 1660 µs

tSKEW1

(Figure 6) Skew Time. The Time Difference

between C12 and GPIO2

Measurements, Command =

ADCVAX

Fast Mode l189 208 221 µs

Normal Mode l493 543 576 µs

tSKEW2

(Figure 3) Skew Time. The Time

Difference between C12 and C0

Measurements, Command = ADCV

Fast Mode l211 233 248 µs

Normal Mode l609 670 711 µs

tWAKE Regulator Start-Up Time VREG Generated from Drive Pin (Figure 28) l100 300 µs

tSLEEP Watchdog or Software Discharge

Timer SWTEN Pin = 0 or DCTO[3:0] = 0000 l1.8 2 2.2 sec

SWTEN Pin = 1 and DCTO[3:0] ≠ 0000 0.5 120 min

tREFUP

(Figure1,

Figures 3 to 7)

Reference Wake-Up Time State: Core = STANDBY l2.7 3.5 4.4 ms

State: Core = REFUP l0 ms

fSADC Clock Frequency l3.0 3.3 3.5 MHz

SPI Interface DC Specifications

VIH(SPI) SPI Pin Digital Input Voltage High Pins CSB, SCK, SDI l2.3 V

VIL(SPI) SPI Pin Digital Input Voltage Low Pins CSB, SCK, SDI l0.8 V

VIH(CFG) Configuration Pin Digital

Input Voltage High Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l2.7 V

VIL(CFG) Configuration Pin Digital

Input Voltage Low Pins ISOMD, SWTEN, GPIO1 to GPIO5, A0 to A3 l1.2 V

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2

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elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ILEAK(DIG) Digital Input Current Pins CSB, SCK, SDI, ISOMD, SWTEN,

A0 to A3

l±1 µA

VOL(SDO) Digital Output Low Pin SDO Sinking 1mA l0.3 V

isoSPI DC Specifications (See Figure 16)

VBIAS Voltage on IBIAS Pin READY/ACTIVE State

IDLE State

l1.9 2.0

02.1 V

IBIsolated Interface Bias Current RBIAS = 2k to 20k l0.1 1.0 mA

AIB Isolated Interface Current Gain VA≤ 1.6V IB= 1mA

IB= 0.1mA

18 20

20 22

24.5 mA/mA

mA/mA

VATransmitter Pulse Amplitude VA= |VIP – VIM|l1.6 V

VICMP Threshold-Setting Voltage on ICMP

Pin VTCMP = ATCMP •VICMP l0.2 1.5 V

ILEAK(ICMP) Input Leakage Current on ICMP Pin VICMP = 0V to VREG l±1 µA

ILEAK(IP/IM) Leakage Current on IP and IM Pins IDLE State, VIP or VIM = 0V to VREG l±1 µA

ATCMP Receiver Comparator Threshold

Voltage Gain VCM = VREG/2 to VREG – 0.2V, VICMP = 0.2V to 1.5V l0.4 0.5 0.6 V/V

VCM Receiver Common Mode Bias IP/IM Not Driving (VREG – VICMP/3 – 167mV) V

RIN Receiver Input Resistance Single-Ended to IPA, IMA, IPB, IMB l27 35 43 kΩ

isoSPI Idle/Wakeup Specifications (See Figure 21)

VWAKE Differential Wake-Up Voltage tDWELL = 240ns l200 mV

tDWELL Dwell Time at VWAKE Before Wake

Detection VWAKE = 200mV l240 ns

tREADY Startup Time After Wake Detection l10 µs

tIDLE Idle Timeout Duration l4.3 5.5 6.7 ms

isoSPI Pulse Timing Specifications (See Figure 19)

t1/2PW(CS) Chip-Select Half-Pulse Width l120 150 180 ns

tINV(CS) Chip-Select Pulse Inversion Delay l200 ns

t1/2PW(D) Data Half-Pulse Width l40 50 60 ns

tINV(D) Data Pulse Inversion Delay l70 ns

SPI Timing Requirements (See Figure 15 and Figure 20)

tCLK SCK Period (Note 4) l1 µs

t1SDI Setup Time before SCK Rising

Edge

l25 ns

t2SDI Hold Time after SCK Rising

Edge

l25 ns

t3SCK Low tCLK = t3+ t4≥ 1µs l200 ns

t4SCK High tCLK = t3+ t4≥ 1µs l200 ns

t5CSB Rising Edge to CSB Falling

Edge

l0.65 µs

t6SCK Rising Edge to CSB Rising

Edge (Note 4) l0.8 µs

t7CSB Falling Edge to SCK Rising

Edge (Note 4) l1 µs

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

LTC6804-1/LTC6804-2

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elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

isoSPI Timing Specifications (See Figure 19)

t8SCK Falling Edge to SDO Valid (Note 5) l60 ns

t9SCK Rising Edge to Short ±1

Transmit

l50 ns

t10 CSB Transition to Long ±1 Transmit l60 ns

t11 CSB Rising Edge to SDO Rising (Note 5) l200 ns

tRTN Data Return Delay l430 525 ns

tDSY(CS) Chip-Select Daisy-Chain Delay l150 200 ns

tDSY(D) Data Daisy-Chain Delay l300 360 ns

tLAG Data Daisy-Chain Lag (vs Chip-

Select)

l0 35 70 ns

t6(GOV) Data to Chip-Select Pulse Governor l0.8 1.05 µs

The ldenotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA= 25°C. The test conditions are V+= 39.6V, VREG = 5.0V unless otherwise noted.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The ADC specifications are guaranteed by the Total Measurement

Error specification.

Note 3: The ACTIVE state current is calculated from DC measurements.

The ACTIVE state current is the additional average supply current into

VREG when there is continuous 1MHz communications on the isoSPI ports

with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply

current. See Applications Information section for additional details.

Note 4: These timing specifications are dependent on the delay through

the cable, and include allowances for 50ns of delay each direction. 50ns

corresponds to 10m of CAT-5 cable (which has a velocity of propagation of

66% the speed of light). Use of longer cables would require derating these

specs by the amount of additional delay.

Note 5: These specifications do not include rise or fall time of SDO. While

fall time (typically 5ns due to the internal pull-down transistor) is not a

concern, rising-edge transition time tRISE is dependent on the pull-up

resistance and load capacitance on the SDO pin. The time constant must

be chosen such that SDO meets the setup time requirements of the MCU.

Note 6: V+needs to be greater than or equal to the highest C(n) voltage for

accurate measurements. See the graph Top Cell Measurement Error vs V+.

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Measurement Error vs Input,

Normal Mode

Measurement Error vs Input,

Filtered Mode

Measurement Error vs Input,

Fast Mode

Measurement Error

vs Temperature

Measurement Error Due to IR

Reflow

Measurement Error Long-

Term Drift

Typical perForMance characTerisTics

Measurement Noise vs Input,

Normal Mode

Measurement Noise vs Input,

Filtered Mode

Measurement Noise vs Input,

Fast Mode

TA= 25°C, unless otherwise noted.

TEMPERATURE (°C)

–50

MEASUREMENT ERROR (mV)

1.5

680412 G01

–1.0

–25 0 50

–1.5

–2.0

2.0

1.0

0.5

–0.5

75 100 125

CELL VOLTAGE = 3.3V

5 TYPICAL UNITS

CHANGE IN GAIN ERROR (ppm)

–125

NUMBER OF PARTS

25 50 75–50 –25 0

680412 G02

–100 –75

35 260°C, 1 CYCLE

TIME (HOURS)

MEASUREMENT ERROR (ppm)

680412 G03

30001000 2000 2500500 1500

CELL VOLTAGE = 3.3V

8 TYPICAL PARTS

INPUT (V)

MEASUREMENT ERROR (mV)

–0.5

0.5

680412 G04

–1.0

–1.5

–2.0 1 2 4

1.0

1.5

2.0 10 ADC MEASUREMENTS

AVERAGED AT EACH INPUT

INPUT (V)

MEASUREMENT ERROR (mV)

–0.5

0.5

680412 G05

–1.0

–1.5

–2.0 1 2 4

1.0

1.5

2.0

INPUT (V)

MEASUREMENT ERROR (mV)

680412 G06

–2

–6

–4

–8

–10 1235

10 ADC MEASUREMENTS

AVERAGED AT EACH INPUT

INPUT (V)

PEAK NOISE (mV)

0.6

0.8

1.0

680412 G07

0.4

0.2

0.5

0.7

0.9

0.3

0.1

01235

INPUT (V)

PEAK NOISE (mV)

0.6

0.8

1.0

680412 G08

0.4

0.2

0.5

0.7

0.9

0.3

0.1

01235

INPUT (V)

PEAK NOISE (mV)

680412 G09

0123

Ce manuel convient aux modèles suivants

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