GOWIN GW1NSE Series Manuel utilisateur
GW1NSE series of SecureFPGA Products
Package & Pinout User Guide
UG874-1.0E, 06/28/2019
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Revision History
Date
Version
Description
06/28/2019
1.0E
Initial version published.
Contents
UG874-1.0E
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Contents
Contents.................................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1 About This Guide.............................................................................................1
1.1 Purpose ..............................................................................................................................1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................2
1.4 Support and Feedback .......................................................................................................2
2 Overview...........................................................................................................3
2.1 PB-Free Package ............................................................................................................... 3
2.2 Package and Max. User I/O Information ............................................................................ 3
2.3 Power Pin ...........................................................................................................................4
2.4 Pin Quantity ........................................................................................................................5
2.4.1 Quantity of GW1NSE-2C Pins......................................................................................... 5
2.5 Pin Definitions.....................................................................................................................5
2.6 I/O BANK Introduction ........................................................................................................8
3 View of Pin Distribution ................................................................................10
3.1 View of GW1NSE-2C Pins Distribution .............................................................................11
3.1.1 View of QN48 Pins Distribution ......................................................................................11
3.1.2 View of LQ144Pins Distribution .....................................................................................12
4 Package Diagrams.........................................................................................13
4.1 QN48 Package Outline (6mm x 6mm)..............................................................................13
4.2 LQ144 Package Outline (22mm x 22mm) ........................................................................14
List of Figures
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List of Figures
Figure 2-1 GW1NSE series of SecureFPGA Products I/O Bank Distribution.................................... 8
Figure 3-1 View of GW1NSE-2C QN48 Pins Distribution (Top View)................................................ 11
Figure 3-2 View of GW1NSE-2C LQ144 Pins Distribution (Top View) ..............................................12
Figure 4-1 Package Outline QN48..................................................................................................... 13
Figure 4-2 LQ144 Package Outline ...................................................................................................14
List of Tables
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List of Tables
Table 1-1 Abbreviation and Terminology............................................................................................ 2
Table 2-1 Package, Max. User I/O Information, and LVDS Paris ......................................................3
Table 2-2 GW1NSE Power Pins ........................................................................................................ 4
Table 2-3 Quantity of GW1NSE-2CPins .............................................................................................5
Table 2-4 Definition of the Pins in the GW1NSE series of FPGA products ....................................... 6
Table 3-1 Other pins in GW1NSE-2C QN48......................................................................................11
Table 3-2 Other pins in GW1NSE-2C LQ144 ....................................................................................12
1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NSE series of
SecureFPGA products together with a definition of the pins, list of pin
numbers, distribution of pins, and package diagrams.
1.2 Related Documents
The user guides are available on the GOWINSEMI Website. You can
find the related documents at www.gowinsemi.com:
1. DS871, GW1NSE series of SecureFPGA products Data Sheet
2. UG290, Gowin FPGA products Programming and Configuration User
Guide
3. UG874, GW1NSE series of SecureFPGA products Package and
Pinout
4. UG872, GW1NSE-2C Pinout
1 About This Guide
1.3 Terminology and Abbreviations
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1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
below Table 1-1 .
Table 1-1 Abbreviation and Terminology
Terminology and Abbreviations
Full Name
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable IO
QN48
QFN48
LQ144
LQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:[email protected]
2 Overview
2.1 PB-Free Package
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2Overview
GOWIN SecureFPGA products provide a Root of Trust based on
SRAM PUF technology. Each device is factory provisioned with a unique
key pair that is never exposed outside of the device or to the internal
development space. The Intrinsic ID BroadKey-Pro security library is
provided with GOWIN SecureFPGA devices allowing easy integration of
common security features into user applications. The GOWIN
SecureFPGA feature set is widely applicable and can used for a variety of
consumer and industrial IoT, edge, and server management applications.
2.1 PB-Free Package
The GW1NSE series of SecureFPGA products are PB free in line with
the EU ROHS environmental directives. The substances used in the
GW1NSE series of SecureFPGA products are in full compliance with the
IPC-1752 standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package, Max. User I/O Information, and LVDS Paris
Package
Pitch (mm)
Size (mm)
GW1NSE-2C
QN48
0.4
6 x 6
39(7)
LQ144
0.5
22 x 22
91(11)
Note!
In this manual, abbreviations are employed to refer to the package types. See
1.3Terminology and Abbreviations.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O; When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one.
2 Overview
2.3 Power Pin
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2.3 Power Pin
Table 2-2 GW1NSE Power Pins
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
VCCPLL
VCCP
Ce manuel convient aux modèles suivants
2
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