FPGANETWORKING SGA10GD Manuel utilisateur
SGA10GD
Dual 10Gbps PCI Expressx8
Ethernet adapter
REFERENCE MANUAL
Ver.: 2009.09.29., Ver. 1.1
(C) BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONO ICS
DEPART ENT OF TELECO UNICATIONS AND EDIA
INFOR ATICS
1
C ntents
Contents...........................................................................................................................................................................................2
1. Introduction..................................................................................................................................................................................3
1.1 What is SGA10GD?...............................................................................................................................................................3
1.2 What is on-board?..................................................................................................................................................................3
1.3 Conformity.............................................................................................................................................................................
2. Architecture..................................................................................................................................................................................5
2.1 Power Supply.........................................................................................................................................................................6
2.2 Clock sources.........................................................................................................................................................................7
2.3 Dual XFPs for 10Gbps Ethernet............................................................................................................................................8
2. PCI Express x8 endpoint......................................................................................................................................................10
2.5 DDR2 SODIMM RAM........................................................................................................................................................12
2.6 Feature Connector................................................................................................................................................................1
2.7 FPGA Programming.............................................................................................................................................................16
2.7.1 Programming through JTAG.........................................................................................................................................16
2.7.2 Programming from FLASH..........................................................................................................................................16
2.7.3 Partial reconfiguration...................................................................................................................................................17
2.8 Status LEDs.........................................................................................................................................................................17
. FPGA test Cores.........................................................................................................................................................................18
.1 PCIEX - Endpoint Block for PCI Express v. 1.6...............................................................................................................18
.2 XAUI v. 8.1..........................................................................................................................................................................18
.3 DDR2 - MIG v. 2.0 generated SODIMM teszt core............................................................................................................18
. Clock domains......................................................................................................................................................................19
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1. Intr ducti n
1.1 What is SGA10GD?
SGA10GD is a PCI-Express x8 adapter card, primarily developed for 10Gbits
Ethernet network monitoring. It's on-board resources, and reconfigurability of its
FPGA extends its functionality beyond the 10G application,
1.2 What is n-b ard?
The figures below show the major on-board components.
Top side components:
1: Dual 10 Gigabit/sec XFP receptacle
2: DDR2 RA SODI Receptacle 1.8V
(Notebook RA )
3: PCI Express x8 Edge Connector
4: Platform FLASH with initial FPGA core
5: 40 pin Berg type Feature Connector
10: XAUI/XFI converters
6: Xilinx Virtex-5 family FPGA device
7: Switching regulators for 1.0, 1.8, 2.5,
3.3 Volts
8: JTAG connector for programming the
FPGA or Flash
9: Interface status LED's, RED/GREEN
pairs
11: Power connector
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1.3 C nf rmity
SGA10GD aims the following Standards/Recommendations:
XFP 10 Gigabit Small F rm Fact r Pluggable M dule
SFF Committee INF-8077i 10 Gigabit Small Form Factor Pluggable odule
...GBE Gigabit Ethernet (Optical/C pper)
IEEE Std 802.3 Carrier sense multiple access with collision detection
(CS A/CD) access method and physical layer specifications
PCIE PCI Express
PCI-SIG PCI Express Base Specification Revision 1.0a
PCI-SIG PCI Express Card Electromechanical Specification Revision 1.0a
DDR2 Dual DataRate II. SDRAM and M dules
JEDEC JESD79-2D DDR2 SDRA SPECIFICATION
JEDEC No.21C 4.20.11 200-Pin DDR2 SDRA Unbuffered SODI Design
Specification. (Item #2017.10) Release No. 17
FC 40 pin Feature C nnect r
...PDH ITU-T G.703 Physical/electrical characteristics of hierarchical digital interfaces
(.9 with passive feature card)
...HDD NCITS 361-2002 AT Attachment with Packet Interface - 6
(ATA/ATAPI-6/UD A5/UD A100/UATA100 interface)
2. Architecture
The simple and robust architecture of SGA10GD is shown on the block diagram
below.
The heart of the board is a Xilinx Virtex-5 family FPGA device.
The PCB can accomodate two types of devices:
XC5VLX110T-2FF1136C (for SGA10GD board)
XC5VLX50T-1FF1136C (for SGA10GDL board)
The main characteristics of the devices are shown in the table below:
XC5VLX110TXC5VLX50T
Array metric 160x54 120x30
Slices 17280 7200
LUT RAM 1120 kBytes 480 kBytes
Bl ck RAM 5.32 Bytes 2.16 Bytes
DSP slices 64 48
GTP Transceivers 16 (8 pairs) 12 (6 pairs)
Cl ck Management Tiles8 6
5
In addition, both types have
Clock anagement Tiles (C Ts) having two Digital Clock anagers (DC )
and a Phase Locked Loop per C T
One PCI Express Endpoint Controller
4 Tri-mode (10/100/1000)Ethernet edia Access Controller ( AC)
2 Internal Configuration Acces Ports (ICAP)
Core logic can run at 550 Hz internal clock speed
Two SGA10GD models can be produced depending on the insertion of FPGA type as
shown below:
M del FPGA
SGA10GD XC5VLX110T
SGA10GDLXC5VLX50T
The following sections detail the rest of the board's architectual elements.
2.1 P wer Supply
The figure below shows the power distribution tree for SGA10GD.
The first stages consist of switching regulator modules (SWR), since on second
stages there are low drop-out (LDO) point of load (POL) type regulators.
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The signal names, nominal voltages, maximum load current, and designated targets
are the following:
Signal name V A Targets N tes
VCC1 1.010FPGA Core voltage
VCC1V8 1.810DDR2 RA ain supply
. . LDO Feed for DDR2 Ref.
. . FPGA I/O Bank 11,13,15,17,(19,21)
. . FLASH Internal voltage
VCC2V5 2.510LDO Feed For GT LDOs
. . FPGA Auxiliary voltage
. . XFP/XAUI Auxiliary voltage
VCC3V3 3.310XFPs .
. . FPGA I/O Bank 20,1,3,0,2,4,(12,5,23,18,6,25)
. . Feature Conn.for I/O std. only
. . FLASH/JTAG I/O voltage
. . DDR2 Supply SPD RO
VCC0V9 0.93 DDR2 Reference voltage
AVCC1 1.03 FPGA GT GT's core voltage
AVCPLL1V2 1.23 FPGA GT GT's PLL supply
VCC5 5 . XFP aux. XPF aux. power
VCC1V2 1.222XFP/XAUI XFP/XAUI converter ain supply
2.2 Cl ck s urces
There are three clock sources available on SGA10GD for the FPGA cores. The
following tables shows their name, nominal frequencies, designated FPGA pins, and
their application.
Signal f [MHz]FPGA# Applicati n
GCLKN 200.00 L18 System/Global Clock, and
GCLKP (XO) K17 DDR2 reference clock
REF2CKN *156.25 H3 XFP Gigabit Ethernet App.
REF2CKP (XO) H4
GT3RCKN *100.00 Y3 PCI Express Hosts reference
GT3RCKP - Y4 .
* These clock references are routed to GT clock pins.
XO designates LVPECL Crystal Oscillators.
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2.3 Dual XFPs f r 10Gbps Ethernet
The SGA10GD board has two XFP module cages (P1,P2) that support user-installed
XFP modules for Gigabit Ethernet (10Gbps) interfaces.
Dedicated 156.25 Hz reference clock source is available for FPGA reference, and
and other XO reference for XAUI/XFI converter chips.
The SGA10GD board provides filtered 1,8V, 3.3V, 5V, power to both XFP modules as
per the XFP specification.
The table below lists the connectors pins and any associated FPGA connectivity.
Status LED's are also listed here.
Signal (P1) XFP#FPGA# Signal (P2) XFP#FPGA#
HSTDP[0] 029 G12 * HSTDP[1] 029 G12 *
HSTDN[0] 028 F12 * HSTDN[1] 028 F12 *
HSRDP[0] 018 C12 * HSRDP[1] 018 C12 *
HSRDN[0] 017 B12 * HSRDN[1] 017 B12 *
HSTCLKP[0]024 G12 * HSTCLKP[1]024 G12 *
HSTCLKN[0]025 F12 * HSTCLKN[1]025 F12 *
GND 001 - GND 001 -
GND 007 - GND 007 -
GND 015 - GND 015 -
GND 016 - GND 016 -
GND 019 - GND 019 -
GND 023 - GND 023 -
GND 026 - GND 026 -
GND 027 - GND 027 -
GND 030 - GND 030 -
VCC5 006 - VCC5 006 -
VCC3V3 008 - VCC3V3 008 -
VCC3V3 009 - VCC3V3 009 -
VCC1V8 020 - VCC1V8 020 -
VCC1V8 022 - VCC1V8 022 -
XINTN[0] 004 E13 XINTN[1] 004 D11
XTXDIS[0] 005 G12 XTXDIS[1] 005 E11
XSCSN[0] 003 E12 XSCSN[1] 003 D10
XSCLK 010 D12 010
XSDIO 011 B12 011
XPLUGN[0] 012 C13 XPLUGN[1] 012 F9
XLOS[0] 014 B13 XLOS[1] 014 E8
XNRDY[0] 013 C12 XNRDY[1] 013 E9
LEDACTN[0]- G13 LEDACTN[1]- G11
LEDLOSN[0]- F13 LEDLOSN[1]- F11
* Routed to the XFAUI/XFI converters U12, U14
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The table below lists the XAUI/XFI converter vs. FPGA connectivity.
C mm n Signal Functi n FPGA#
PRTAD[0] Port base address 0AJ11
PRTAD[1] Port base address 1AP12
PRTAD[2] Port base address 2AK11
PRTAD[3] Port base address 3AN12
PRTAD[4] Port base address 4A 11
U12 Signals Functi n FPGA# U14 Signals Functi n FPGA#
TRSTN[0] Reset (active low) AN14 TRSTN[1] Reset (active low) AF11
DIO[0] DIO data A 13 DIO[1] DIO data AL10
DC[0] DIO clock A 12 DC[1] DIO clock AJ10
CDRLOL[0] Loss of Lock in CDR AP14 CDRLOL[1] Loss of Lock in CDRAE11
C ULOL[0] Loss of Lock in C UAN13 C ULOL[1] Loss of Lock in C UAH10
TTXON[0] TX enable AL11 TTXON[1] TX enable AG11
RXDP[0][0] XAUI RX lane 0 D1 RXDP[1][0] XAUI RX lane 0 T1
RXDN[0][0] C1 RXDN[1][0] R1
RXDP[0][1] XAUI RX lane 1 A3 RXDP[1][1] XAUI RX lane 1 N1
RXDN[0][1] A2 RXDN[1][1] P1
RXDP[0][2] XAUI RX lane 2 A6 RXDP[1][2] XAUI RX lane 2 K1
RXDN[0][2] A7 RXDN[1][2] J1
RXDP[0][3] XAUI RX lane 3 A9 RXDP[1][3] XAUI RX lane 3 G1
RXDN[0][3] A8 RXDN[1][3] H1
TXDP[0][0] XAUI TX lane 0 E2 TXDP[1][0] XAUI TX lane 0 U2
TXDN[0][0] D2 TXDN[1][0] T2
TXDP[0][1] XAUI TX lane 1 B4 TXDP[1][1] XAUI TX lane 1 2
TXDN[0][1] B3 TXDN[1][1] N2
TXDP[0][2] XAUI TX lane 2 B5 TXDP[1][2] XAUI TX lane 2 L2
TXDN[0][2] B6 TXDN[1][2] K2
TXDP[0][3] XAUI TX lane 3 B10 TXDP[1][3] XAUI TX lane 3 F2
TXDN[0][3] B9 TXDN[1][3] G2
* RXPOLARITY attribute for the GT has to be changed
** TXPOLARITY attribute for the GT has to be changed
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2.4 PCI Express x8 endp int
The PCI Express endpoint connector (designated as J1 on-board) allows an FPGA
design to support x1, x4 and x8 gigabit lanes to communicate with the host, at the
speed of 2.5 Gbps of each.
Caution! There are jumpers - designated as J2, J9 - on board to select the proper
presence detect lane configuration (close J2 for x4, plus close J9 for x8) for the
actual design.
The table below lists the connectors pins and any associated FPGA connectivity.
Signal (P1) Side A FPGA# Signal (P2) Side B FPGA#
PRESENT_NA1 - +12 VOLTS B1 To PWR
+12 VOLTS A2 To PWR +12 VOLTS B2 To PWR
+12 VOLTS A3 To PWR +12 VOLTS B3 To PWR
GND A4 - GND B4 -
JTAG_TCK A5 - S CLK B5 -
JTAG_TDI A6 - S DAT B6 -
JTAG_TDO A7 - GND B7 -
JTAG_T S A8 - +3.3 VOLTS B8 -
+3.3 VOLTS A9 - JTAG_TRST_N B9 -
+3.3 VOLTS A10 - +3.3 VAUX B10 -
PXPERST A11 - PCIE_WAKE_NB11 -
KEY KEY KEY KEY KEY KEY
GND A12 - RESERVED B12 -
PXCLKP A13 Y4 GND B13 -
PXCLKN A14 Y3 PETP0 B14 W1
GND A15 - PETN0 B15 Y1
PERP0 A16 V2 GND B16 -
PERN0 A17 W2 PRESENT_N B17 -
GND A18 - GND B18 -
RESERVED A19 - PETP1 B19 AA1 **
GND A20 - PETN1 B20 AB1
PERP1 A21 AB2 * GND B21 -
PERN1 A22 AC2 GND B22 -
GND A23 - PETP2 B23 AE1
GND A24 - PETN2 B24 AF1
PERP2 A25 AD2 GND B25 -
PERN2 A26 AE2 GND B26 -
GND A27 - PETP3 B27 AG1 **
GND A28 - PETN3 B28 AH1
PERP3 A29 AH2 * GND B29 -
PERN3 A30 AJ2 --- B30 -
GND A31 - PRESENT4_N B31 To J2
--- --- - GND B32 -
--- --- - PETP4 B33 AL1
GND A34 - PETN4 B34 A 1
PERP4 A35 AK2 GND B35 -
PERN4 A36 AL2 GND B36 -
GND A37 - PETP5 B37 AP2 **
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Table des matières
