Exar XRT71D00 Manuel utilisateur

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

DESIGNING THE XRT71D00 AND THE XRT73L00

DEVICES TO OPERATE IN THE HOST MODE, AND TO

BE ACCESSED VIA A SINGLE CHIP SELECT PIN

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

DESIGNING THE XRT71D00 AND THE XRT73L00

DEVICES TO OPERATE IN THE HOST MODE, AND TO

BE ACCESSED VIA A SINGLE CHIP SELECT PIN

TABLE OF CONTENTS

TABLE OF CONTENTS............................................................................................................................... 2

1.0 INTRODUCTION .................................................................................................................................. 3

2.0 BACKGROUND INFORMATION ON THE XRT73L00 AND XRT71D00 DEVICES...................... 4

2.1 BACKGROUND INFORMATION – THE XRT73L00 1-CHANNEL DS3/E3/STS-1 LIU IC ...... 4

2.2 BACKGROUND INFORMATION – THE XRT71D00 1-CHANNEL DS3/E3/STS-1 JITTER

ATTENUATOR IC ................................................................................................................................... 7

3.0 THE CHANNEL ASSIGNMENT FEATURE OF THE XRT71D00 DEVICE................................... 9

4.0 HARDWARE DESIGN CONSIDERATIONS .................................................................................... 12

4.1 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE

RECEIVE PATH.................................................................................................................................... 15

4.2 DESIGN CONSIDERATIONS WHEN THE JITTER ATTENUATOR IS DESIGNED IN THE

TRANSMIT PATH................................................................................................................................. 18

5.0 POWER CONDITION CONSIDERATIONS FOR THE XRT73L00 AND THE XRT71D00

DEVICES..................................................................................................................................................... 21

6.0 THE BNC CONNECTOR SHIELDS.................................................................................................. 27

APPENDIX A – REGISTER DESCRIPTION FOR THE XRT73L00 DS3/E3/STS-1 LIU IC ............... 28

APPENDIX B – REGISTER DESCRIPTION FOR THE XRT71D00 DS3/E3/STS-1 JITTER

ATTENUATOR IC...................................................................................................................................... 39

APPENDIX C – DESCRIPTION OF MICROPROCESSOR SERIAL INTERFACE PINS................... 44

C.1 A BRIEF DESCRIPTION OF THE MICROPROCESSOR SERIAL INTERFACE PINS........ 45

C.2 USING THE MICROPROCESSOR SERIAL INTERFACE........................................................ 47

APPENDIX D - CONTACT INFORMATION FOR API-DELEVAN: .................................................... 50

APPENDIX E – REVISION CHANGE HISTORY ................................................................................... 51

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

1.0 INTRODUCTION

The purpose of this Applications Note is two-fold.

a. To describe a possible approach that one can use to interface the XRT71D00

DS3/E3/STS-1 Jitter Attenuator to the XRT73L00 DS3/E3/STS-1 LIU IC, while

operating each device in the “Host” Mode. In particular, this Applications Note

describes how to design a system, such that a Microprocessor can perform

READ/WRITE access to both the XRT71D00 and the XRT73L00 device with a

single Chip-Select (CS) signal.

b. To provide some “Power Conditioning” recommendations for designs using the

XRT71D00 and the XRT73L00 devices.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

2.0 BACKGROUND INFORMATION ON THE XRT73L00

AND XRT71D00 DEVICES

The next couple of sections present a detailed description of both the XRT73L00 and the

XRT71D00 devices.

2.1 BACKGROUND INFORMATION – THE XRT73L00 1-

CHANNEL DS3/E3/STS-1 LIU IC

The XRT73L00 device is a single Channel DS3/E3/STS-1 LIU IC that was designed to

operate at 3.3V. Further this device can be configured via two possible approaches.

a. The Hardware Mode

b. The Host Mode.

If the XRT73L00 device has been configured to operate in the “Hardware” Mode, then

all Mode/Configuration selection is achieved by setting certain input pins either “HIGH”

or “LOW”. If the user configures the XRT73L00 device to operate in the “Hardware”

Mode, then the user can configure the XRT73L00 device into a wide variety of modes,

via the following external input pins.

•REQDIS – Receive Equalizer Enable/Disable Input pin

•TXLEV – Transmit Line Build-Out Circuit Enable/Disable Input pin.

•LLB & RLB – Loop Mode Select input pins.

•STS-1/DS3* & E3 – Data Rate Select Input pins.

•ENDECDIS – B3ZS/HDB3 Encoder & Decoder Block Enable/Disable Input pin.

•DR/SR* - Dual-Rail/Single-Rail Select Input pin.

•TxOFF – Transmit Shut Off Input pin.

•TAOS – Transmit All Ones Enable Input pin

•RCLK2INV – RCLK2 Invert/Non-Invert Select Input pin.

Therefore, for Hardware Mode operation, the XRT73L00 device provides the user with

11 input pins that can be used to control various operational aspects of the XRT73L00

device.

If the XRT73L00 device has been configured to operate in the Host Mode, then all

Mode/Configuration selection is achieved by writing data into the on-chip Command

Registers (via the Microprocessor Serial Interface block). The Microprocessor Serial

Interface block consists of the following pins.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

•SDI – Serial Data In

•SDO – Serial Data Out

•SCLK – Serial Clock In

•CS* - Chip Select Input

•REG_RESET* - Register Reset Input.

A more detailed description of each of these pins is presented in Appendix C.

Therefore, for Host Mode operation, the XRT73L00 device provides the user with 5 pins

(4 input and 1 output) that can be used to control various operational aspects of the

XRT73L00 device.

The bit-format of the Command Register set, within the XRT73L00 LIU device is

presented below in Figure 1.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

Address Command

0x00 CR0 RO RLOL RLOS ALOS DLOS DMO

0x01 CR1 R/W TXOFF TAOS TXCLKINV TXLEV TXBIN

0x02 CR2 R/W Reserved ENDECDIS ALOSDIS DLOSDIS REQDIS

0x03 CR3 R/W RNRZ LOSMUT RCLK2/

LCV* RCLK2INV RCLK1INV

0x04 CR4 R/W Reserved STS-1/

DS3* E3 LLB RLB

0x05 CR5 R/W Reserved Reserved Reserved Reserved Reserved

0x06 CR6 R/W Reserved Reserved Reserved Reserved Reserved

0x07 CR7 R/W Reserved Reserved Reserved Reserved Reserved

0x08 CR8 R/W Reserved Reserved Reserved Reserved Reserved

Figure 1, The Bit Format of the Command Registers, within the XRT73L00 Device.

A detailed discussion of each of these command register bits is presented in Appendix A.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

2.2 BACKGROUND INFORMATION – THE XRT71D00 1-

CHANNEL DS3/E3/STS-1 JITTER ATTENUATOR IC

The XRT71D00 device is a single-channel DS3/E3/STS-1 Jitter Attenuator IC that was

designed to operate at either 3.3V or 5V. Further, this device can be configured via two

possible approaches.

a. The Hardware Mode

b. The Host Mode

If the XRT71D00 device has been configured to operate in the “Hardware” Mode, then

all Mode/Configuration selection is achieved by setting certain input pins either “HIGH”

or “LOW”. If the user configures the XRT71D00 device to operate in the “Hardware”

Mode, the user can configure the XRT71D00 device into a wide variety of modes, via the

following external input pins.

•FSS – FIFO Size Select

•DJA – Disable (Jitter Attenuator PLL) Select

•CLKES – Clock Edge Select

•BWS – (Jitter Attenuator PLL) Bandwidth Select

•DS3*/E3 – Data Rate Select Input pin

•STS-1 – Data Rate Select Input pin.

Therefore, for Hardware Mode operation, the XRT71D00 device provides the user with 6

input pins that can be used to control various operational aspects of the XRT71D00

device.

If the XRT71D00 device has been configured to operate in the “Host” Mode, then all

Mode/Configuration is achieved by writing data into the on-chip Command Registers

(via the Microprocessor Serial Interface block). The Microprocessor Serial Interface

block consists of the following pins.

•SDI – Serial Data In

•SDO – Serial Data Out

•SCLK – Serial Clock Input

•CS* - Chip Select Input

•RST* - Reset Input

A more detailed description of each of these pins is presented in Appendix C.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

Therefore, for Host Mode Operation, the XRT71D00 device provides the user with five

(5) pins (4 inputs and 1 output) that can be used to control various aspects of the

XRT71D00 device.

The bit-format of the Command Register set, within the XRT71D00 Jitter Attenuator

device is presented below in Figure 2.

Addr. Command

D3 D2 D1 D0

Channel 0 Registers

0x06 CR6 R/W STS-1 0 E3/DS3* DJA BWS CLKES FSS

0x07 CR7 R/O Reserved Reserved Reserved Reserved Reserved Reserved FL

Channel 1 Registers

0x0E CR14 R/W STS-1 0 E3/DS3* DJA BWS CLKES FSS

0x0F CR15 R/W Reserved Reserved Reserved Reserved Reserved Reserved FL

Channel 2 Registers

0x16 CR22 R/W STS-1 0 E3/DS3* DJA BWS CLKES FSS

0x17 CR23 R/W Reserved Reserved Reserved Reserved Reserved Reserved FL

Figure 2, The Bit Format of the Command Registers, within the XRT71D00 Device.

A detailed discussion of each of these Command Register bits are presented in Appendix

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

3.0 THE CHANNEL ASSIGNMENT FEATURE OF THE

XRT71D00 DEVICE

The “Channel Assignment” feature, within the XRT71D00 device, permits the user to

perform “READ/WRITE” access to the following sets of devices, with only one Chip

Select pin.

•1- XRT73L00 1-Channel DS3/E3/STS-1 LIU IC and 1-XRT71D00 DS3/E3/STS-1

Jitter Attenuator IC.

•1-XRT7300 1-Channel DS3/E3/STS-1 LIU IC and 1-XRT71D00 DS3/E3/STS-1 Jitter

Attenuator IC.

•1- XRT73L02 2-Channel DS3/E3/STS-1 LIU IC and 2-XRT71D00 DS3/E3/STS-1

Jitter Attenuator Devices.

•1-XRT7302 2-Channel DS3/E3/STS-1 LIU IC and 2-XRT71D00 DS3/E3/STS-1 Jitter

Attenuator Devices.

•1-XRT73L03 3-Channel DS3/E3/STS-1 LIU IC and 3-XRT71D00 DS3/E3/STS-1

Jitter Attenuator Devices.

Figure 2 presents the bit format of the Command Registers, within the XRT71D00

device. In this figure, the Command Register set is sub-divided into “Channels”.

Command Registers CR6 and CR7 are allocated to “Channel 0”; Command Registers

CR14 and CR15 are allocated to “Channel 1”; and finally, Command Registers CR22 and

CR23 have been allocated to “Channel 2”. The XRT71D00 device contains two external

input pins, which are relevant to this discussion.

•Ch_Addr_0 (Pin 28)

•Ch_Addr_1 (Pin 15)

A XRT71D00 device (within a given system) can be assigned a “Channel Number” by

setting the “Ch_Addr_0” and “Ch_Addr_1” input pins either high or low. The

relationship between the states of the “Ch_Addr_0” and the “Ch_Addr_1” input pins, and

the “Assigned Channel” is presented below in Table 1.

TAN-042

Designing the XRT71D00 and the XRT73L00 Devices to

operate in the Host Mode, and to be accessed via a single Chip

Select pin.

Preliminary July 19, 2001

Revision 1.03

Table 1, The Relationship between the Logic States of the “Ch_Addr_0” and

“Ch_Addr_1” input pins, and the “Assigned Channel”

Ch_Addr_1 Ch_Addr_0 Assigned Channel

0 0 Channel 0

0 1 Channel 1

1 0 Channel 2

1 1 Not Valid

If a given XRT71D00 device is assigned to “Channel 0” then it will only respond to

READ/WRITE operations to Address locations 0x06 and 0x07 (within the device). If the

Microprocessor attempts to perform write operations to address locations “0x0E” and

“0x16”, then the XRT71D00 device will ignore this particular operation. Further, if the

Microprocessor attempts to perform read operations to address locations “0x0E”, “0x0F”,

“0x16” and “0x17”, then the XRT71D00 device will simply ignore these particular

operations and will continue to tri-state its “SDO” output pin.

Similarly, if a given XRT71D00 device is assigned to “Channel 1” then it will only

respond to READ/WRITE operations to Address locations 0x0E and 0x0F (within the

device). If the Microprocessor attempts to perform write operations to address locations

“0x06” and “0x16”, then the XRT71D00 device will ignore this particular operation.

Further, if the Microprocessor attempts to perform read operations to address locations

“0x06”, “0x07”, “0x16” and “0x17”, then the XRT71D00 device will simply ignore these

particular operations and will continue to tri-state its “SDO” output pin.

This Applications Note discusses how to interface a single XRT71D00 device to the

XRT73L00 device. Therefore, the Jitter Attenuator IC (within this Applications Note)

will be assigned to “Channel 0”.

When the XRT71D00 device has been assigned to “Channel 0” and has been interfaced

with the XRT73L00 device (as shown in Figure 3); then the resulting composite

Command Register Address Map is as presented below.

Ce manuel convient aux modèles suivants

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