Epson SED1352 Manuel utilisateur

SED1352 Graphics LCD Controller

SED1352

TECHNICAL MANUAL

Document Number: X16B-Q-001-06

Information in this document is subject to change without notice. You may download and use this document, but only for your ownuse in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

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Page ii Epson Research and Development

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Epson Research and Development Page iii

Vancouver Design Center

Issue Date: 98/10/08 SED1352

CUSTOMER SUPPORT INFORMATION

Comprehensive Support Tools

Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set ofresources and tools

forthe development of imbedded graphics systems.

Evaluation / Demonstration Board

•Assembled and fully tested graphics evaluation board with installation guide and schematics

•To borrow an evaluation board, please contact yourlocal Seiko Epson Corp. sales representative

Chip Documentation

•Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference

Software

•OEM Utilities

•User Utilities

•Evaluation Software

•To obtain these programs, contact Application Engineering Support

Application Engineering Support

Engineering and Sales Support is provided by:

Japan

Seiko Epson Corporation

ElectronicDevices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Fax: 042-587-5564

http://www.epson.co.jp

Hong Kong

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 2827-4346

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

10F, No.287

Nanking East Road

Sec. 3, Taipei,Taiwan,R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Singapore

Epson Singapore Pte., Ltd.

No.1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Europe

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

NorthAmerica

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134,USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.erd.epson.com

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TABLE OF CONTENTS

INTRODUCTION

SED1352 Graphics LCD Controller Data Sheet

SPECIFICATION

SED1352 Hardware Functional Specification

PROGRAMMER’S REFERENCE

SED1352 Programming Notes and Examples

UTILITIES

1352SHOW.EXE Display Utility

VIRTUAL.EXE Display Utility

BIOS1352.COM Utility

1352GRAY.EXE Display Utility

1352PD.EXE Power Down Utility

1352READ.EXE Diagnostic Utility

EVALUATION

SDU1352B0C Rev 1.0 Evaluation Board User Manual

APPLICATION NOTES

Power Consumption

ISA Bus Interface Considerations

MC68340 Interface Considerations

LCD Panel Options / Memory Requirements

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GRAPHICS

SED1352

X16B-C-001-06 1

October 1998

SED1352 GRAPHICS LCD CONTROLLER

■DESCRIPTION

The SED1352 is a graphics display LCD controller capable of displaying a maximum of 16 levels of gray on single and dual

scan Liquid Crystal Displays. A 16x4 lookup table is provided to allow remapping of the 16 possible gray shades displayed on

the LCD panel. The SED1352 can interface to the MC68000 microprocessor and 8/16 bit MPUs with READY (WAIT#) signal

with minimum external “glue” logic. This chip can directly control up to 128 Kbytes of static SRAM.

Optimized for cost and power savings, the SED1352 can operate from 2.7 volts to 5.5 volts and up to 25MHz.

■FEATURES

•16-bit 16 MHz MC68000 MPU interface

•8/16-bit MPU interface controlled by a READY (or

WAIT#) signal

•option to use built-in index register or direct-mapping to

access one of fifteen internal registers

•2-terminal crystal input for internal or external

crystal oscillator

•8/16-bit SRAM interface configurations

•two software power-save modes

•low power consumption

•display modes:

2 bit/pixel, 4-level gray-scale display

4 bit/pixel, 16-level gray-scale display

•virtual display support

•display memory interface:

one 1 Mbit SRAM(64Kx16)

one or two 32Kbyte SRAM(s)

one or two 8Kbyte SRAM(s)

one 8Kbyte and one 32Kbyte SRAM

•LCD panel configurations:

single-panel, single-drive display

dual-panel, dual-drive display

•maximum number of vertical lines:

1,024 lines (single-panel, single-drive display)

2,048 lines (dual-panel, dual-drive display)

•split screen display support at single-panel mode

•package:

QFP5-100-S2 package (F0B)

or QFP15-100-STD package (F1B)

■SYSTEM BLOCK DIAGRAM

LCD PANEL

MPU SED1352

SRAM

CLOCK

80xx

Z80

68xxx

DATA

CONTROL

ADDRESS

GRAPHICS

SED1352

X16B-C-001-06

■INTERFACE OPTIONS

Note: Example implementation, actual may vary.

SED1352

MEMCS#

IOCS#

MC68xxx

DTACK#

D0 to D15

A1 to A19 AB1 to AB19

DB0 to DB15

IOW#

IOR#

Decoder

AS#

R/W#

BHE#

UDS#

READY

A20 to A23

AB0

LDS#

Decoder

A16.. A14

A10 to A19

FC0 to FC1

Interface with 16-Bit MC68xxx MPU and 16Kbytes SRAM (2 of 8K x 8)

64 Kbit

VWE#

VD0-7

VCS0#

VCS1#

VA0-12

WE#

CS#

64 Kbit

WE#

CS#

VD8-15

MEMCS#

MEMW#

MEMR#

READY

DB0 to DB7

AB0 to AB15

IOCS#

IOW#

IOR#

RESET

SED1352

Z80

RESET#

D0 to D7

WAIT#

A0 to A15

WR#

RD#

Decoder

IORQ#

A10 to A15

Decoder

MREQ#

Interface with 8-Bit Z80 MPU and 16Kbytes SRAM (2 of 8K x 8)

64 Kbit

VWE#

VD0-7

VCS0#

VCS1#

VA0-12

WE#

CS#

64 Kbit

WE#

CS#

MI#

GRAPHICS

SED1352

X16B-C-001-06 3

Note: Example implementation, actual may vary.

8086

(Maximum mode)

CLK

READY

RESET#

RDY

MEMW#

MEMR#

READY

DB0 to DB15

AB0 to AB15

IOW#

IOR#

RESET

SED1352

8284A

D0 to D15

CLK

S2#

S1#

S0#

DEN

MRDC#

AMWC#

IORC#

AIOWC#

DT/R

CLK

READY

RESET#

8288

AB16 to AB19

M/IO#

BHE#

A0 to A16

STB

Decoder

A16 to A19

S2#

S1#

S0#

ALE

BHE#

AD0 to AD15 A16 BHE#

MEMCS#

IOCS#

Interface with 16-Bit 8086 MPU and 64Kbytes SRAM (2 of 32K x 8)

256 Kbit

VWE#

VD0-7

VCS0#

VCS1#

VA0-14

WE#

CS#

256 Kbit

WE#

CS#

VD8-15

Interface with 8-Bit ISA Bus and 40Kbytes SRAM (1 of 8K x 8 and 1 of 32K x 8)

SED1352

MEMCS#

MEMW#

MEMR#

READY

8-Bit ISA Bus

SMEMW#

SMEMR#

IOCHRDY

REFRESH

SA0 to SA19

SD0 to SD7 DB0 to DB7

AB0 to AB19

Decoder

SA16.. SA13

IOCS#

IOW#

IOR#

RESET

RESET#

SA10 to SA15

AEN

IOW#

IOR#

Decoder

0WS#

optional

SA(1 or 4) to SA9

Decoder

64 Kbit

VWE#

VD0-7

VCS0#

VCS1#

VA0-14

WE#

CS#

256 Kbit

WE#

CS#

GRAPHICS

SED1352

X16B-C-001-06

Note: Example implementation, actual may vary.

■SUPPORTED RESOLUTIONS

Display

RAM

Example Display Size SRAM

Type CPU

Interface SRAM

Interface

4 Grays 16 Grays

X Y X Y

8 Kbytes 256 x 128 128 x 128 1 of 8Kx8 8-bit 8-bit

16 Kbytes 320 x 200 200 x 160 2 of 8Kx8 8-bit 8-bit/16-bit

16-bit 16-bit

32 Kbytes 512 x 256 256 x 256 1 of 32Kx8 8-bit 8-bit

40 Kbytes 512 x 320 320 x 256 1 of 8Kx8 and

1 of 32Kx8 8-bit 8-bit

64 Kbytes 512 x 512 512 x 256 2 of 32Kx8 8-bit 8-bit/16-bit

16-bit 16-bit

128 Kbytes 1024 x 512 512 x 512 1 of 64Kx16 16-bit 16-bit

Interface with 16-Bit ISA Bus and 128Kbytes SRAM (1 of 128K x 8)

SED1352

MEMCS#

MEMW#

MEMR#

READY

16-bit ISA Bus

SMEMW#

SMEMR#

IOCHRDY

REFRESH

SA0 to SA19

SD0 to SD15 DB0 to DB15

AB0 to AB19

Decoder

IOCS#

IOW#

IOR#

RESET

RESET#

Decoder

SA10 to SA15

AEN

IOW#

IOR#

IOCS16#

SA(1 or 4) to SA9

BHE#

SBHE#

Decoder

MEMCS16#

LA17 to LA23

SA16.. SA14

Decoder

VWE#

VD0-7

VD8-15

VCS0#

VCS1#

VA0-15

1 Mbit

WE#

UB#

LB#

A0-15

I/O 1-8

I/O 9-16

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