DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
2Final
Version: DM9000-DS-F02
June 26, 2002
Table of Contents
1. General Description ..............................................1
2. Block Diagram……………………………………… 1
3. Features ................................................................4
4. Pin Configuration ..................................................5
4.1 Pin Configuration I: with MII Interface.................5
4.2 Pin Configuration II: with 32-Bit Data Bus...........6
5. Pin Description......................................................7
5.1 MII Interface ........................................................7
5.2 Processor Interface.............................................8
5.3 EEPROM Interface. ............................................9
5.4 Clock Interface ....................................................9
5.5 LED Interface ......................................................9
5.6 10/100 PHY/Fiber .............................................10
5.7 Miscellaneous Pins ...........................................10
5.8 Power Pins........................................................10
6. Vendor Control and Status Register Set.............11
6.1 Network Control Register (00H)........................13
6.2 Network Status Register (01H) .........................13
6.3 TX Control Register (02H) ................................13
6.4 TX Status Register I (03H)................................14
6.5 TX Status Register II (04H)...............................14
6.6 RX Control Register (05H)................................14
6.7 RX Status Register (06H) .................................15
6.8 Receive Overflow Counter Register (07H) .......15
6.9 Back Pressure Threshold Register (08H) .........15
6.10 Flow Control Threshold Register (09H) ..........16
6.11 RX/TX Flow Control Register (0AH) ...............16
6.12 EEPROM & PHY Control Register (0BH) .......16
6.13 ROM & PHY Address Register (0CH) ............17
6.14 EEPROM & PHY Data Register (0DH, 0EH)..17
6.15 Wake Up Control Register (0FH)....................17
6.16 Physical Address Register (10H~15H) ...........17
6.17 Multicast Address Register (16H~1DH)..........18
6.18 General Purpose Control Register (1EH)…….18
6.19 General Purpose Register (1FH) ....................18
6.20 TX SRAM Read Pointer Address Register
(22H~23H) ..............................................................18
6.21 RX SRAM Write Pointer Address Register
(24H~25H) .......................................................19
6.22 Vendor ID Register (28H~29H).......................19
6.23 Product ID Register (2AH~2BH) .....................19
6.24 Chip Revision Register (2CH).........................19
6.25 Special Mode Control Register (2FH).............19
6.26 Memory Data Read Command without Address
Increment Register (F0H) ................................19
6.27 Memory Data Read Command with Address
Increment Register (F2H) ................................19
6.28 Memory Data Read_ address Register
(F4H~F5H) ......................................................19
6.29 Memory Data Write Command without Address
Increment Register (F6H) ................................19
6.30 Memory Data Write Command with Address
Increment Register (F8H) ................................19
6.31 Memory Data Write_ address Register
(FAH~FBH) ......................................................20
6.32 TX Packet Length Register (FCH~FDH) ........20
6.33 Interrupt Status Register (FEH) ......................20
6.34 Interrupt Mask Register (FFH) ........................20
7. EEPROM Format ................................................21
8. MII Register Description......................................22
8.1 Basic Mode Control Register (BMCR) – 00 ......23
8.2 Basic Mode Status Register (BMSR) – 01........24
8.3 PHY ID Identifier Register #1 (PHYID1) – 02 ...25
8.4 PHY Identifier Register #2 (PHYID2) – 03........25
8.5 Auto-negotiation Advertisement Register
(ANAR) – 04 ....................................................26
8.6 Auto-negotiation Link Partner Ability Register
(ANLPAR) – 05 ................................................27
8.7 Auto-negotiation Expansion Register (ANER) –
06 .....................................................................27
8.8 DAVICOM Specified Configuration Register
(DSCR) – 16 .....................................................28
8.9 DAVICOM Specified Configuration and Status
Register (DSCSR) – 17 ...................................29
8.10 10BASE-T Configuration/Status (10BTCSR) –
18.....................................................................30
