Cirrus Logic CS42L42 Manuel utilisateur

http://www.cirrus.com

DS1083F2

AUG ‘17

Low-Power Audio Codec with SoundWire™–I

S/TDM and Audio Processing

System Features

•

Stereo headphone (HP) output with 114-dB dynamic range

— Class H HP amplifier with four-level automatic or

manual supply adjust

— Power output 2 x 35 mW into 30 

• Mono mic input with 114-dB dynamic range

— Low-noise headset bias with integrated bias resistor

—1-V

RMS input voltage

— Integrated AC-coupling capacitors

• Integrated detect features

— OMTP (Open Mobile Terminal Platform) and AHJ

(American headset jack) headset-type detection and

configuration with low-impedance internal switches

— Mic short (S0 Button) detect with ADC automute

— Automatic Hi-Z of headset bias output to ground on

headset bias current rise or HP/headset unplug

• System wake from headset/headphone plug/unplug or

S0 button press

• Interrupt output

• Mono equalizer for side-tone mix

•MIPI

® SoundWire™ or I2C/I2S/TDM control and audio

interface

• S/PDIF transmit (Sony/Philips digital interface format)

• Integrated fractional-N PLL

— Increases system-clock flexibility for audio processing

— Reference clock sourced from either I2S/TDM bit clock

or MIPI SoundWire clock

• Audio serial port (ASP)

—I

2S (two channels) or TDM (up to four channels)

— Slave or Hybrid-Master Mode (bit-clock slave and

LRCK/FSYNC derived from bit clock)

— Sample-rate converter (SRC) for two input channels,

with bypass

— SRC for one output channel, with bypass

— User isochronous audio transport support

— Supports up to 192-kHz sample rate to S/PDIF output

— Sample rate support for 8 to 192 kHz

• Integrated power management

— Digital core operates from either an external 1.2-V

supply or LDO from a 1.8-V supply.

— Step-down charge pump improves HP efficiency

— Independent peripheral power-down controls

— Standby operation from VP with all other supplies

powered off

— VP monitor to detect and report brownout conditions

— Low-impedance switching suppresses ground-noise

Applications

• Ultrabooks, tablets, and smartphones

• Digital headsets

CS42L42

PLL

Clock

Gen

MCLK

HPOUTB

–

VCP_ FILT

MCLK

HPOUTA

+VC P _F I LT

Interpolator

HSIN+

HSIN–



ADC

SWIRE_SD/

ASP_SDIN

SWIRE_CLK/

ASP_SCLK

DAC

ASP_SDOUT ASP_LRCK/

FSYNC

Decimators

Pseudodifferential Input

Headphone Detect

HS4

HS3

HS_CLAMP1

HS_CLAMP2

TIP_SENSE

INT

DAO

SoundWire

Audio and

Control

Port

DAI

SRC SRC SRC

HPF /

Mute

Windnoise

Filter EQ

Headset

Detect,

Switches,

and Depletion

FET Control

Interpolator



Downlink

WAKE

–

VCP_ FILT

+VCP_FILT

HS4_REF

HS3_REF

RING_SENSE

HS Bias LDO

VL VD_FILT

DIGLDO_PDN

+VCP_FILT

–VCP_FILT

Inverting

Step-Down

LDO

Analog

Core

POR

VCP

VP _CP

ADC

Mute

SWIRE_SEL

HPSENSA

Digital

Core

Downlink

–

HPSENSB

–

MCLK

SCLSDA

S/PDIF

C Slave

SPDIF_TXAD0 AD1

LDO

with

Bypass

CS42L42

DS1083F2 2
CS42L42
 
General Description
The CS42L42 is a low-power audio codec with integrated MIPI SoundWire interface or I2C/I2S/TDM interfaces designed 
for portable applications. It provides a high-dynamic range, stereo DAC for audio playback and a mono 
high-dynamic-range ADC for audio capture.
The CS42L42 provides high performance (up to 24-bit) audio for ADC and DAC audio playback and capture functions as 
well as for the S/PDIF transmitter. The CS42L42 architecture includes bypassable SRCs and a bypassable, three-band, 
32-bit parametric equalizer that allows processing of digital audio data.
A digital mixer is used to mix the ADC or serial ports to the DACs. There is independent attenuation on each mixer input.
The processing along the output paths from the ADC or serial port to the two stereo DACs includes volume adjustment
and mute control.
The CS42L42 is available in a 49-ball WLCSP package and a 48-pin QFN package for extended temperature range grade 
of –40°C to +85°C.
Table of Contents
Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . .  3
1 WLCSP Pin Out (Through-Package View)  . . . . . . . . . . . . . .  3
2 QFN Pin Out (Through-Package View)  . . . . . . . . . . . . . . . . .  4
3 Pin Descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
4 Electrostatic Discharge (ESD) Protection Circuitry  . . . . . . . .  7
Typical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
1 Electromagnetic Compatibility (EMC) Circuitry  . . . . . . . . . .  11
Characteristics and Specifications  . . . . . . . . . . . . . . . . . . . . .  12
Functional Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
1 Analog Input   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  31
2 Digital Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
3 Three-Band Equalizer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
4 Analog Output  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
5 System Headphone Parasitic Resistances  . . . . . . . . . . . . .  39
6 Class H Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
7 Clocking Architecture   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
8 SoundWire Interface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  52
9 Audio Serial Port (ASP) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  67
10 S/PDIF Tx Port   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  73
11 Sample-Rate Converters (SRCs)   . . . . . . . . . . . . . . . . . . .  75
12 Headset Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  76
13 Headset Type Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  78
14 Plug Presence Detect  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  79
15 Power-Supply Considerations  . . . . . . . . . . . . . . . . . . . . . .  82
16 Control-Port Operation   . . . . . . . . . . . . . . . . . . . . . . . . . . .  84
17 Reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  86
18 Interrupts  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  87
System Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
1 Power-Up Sequence    . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  89
2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .  92
3 SoundWire Power Sequences   . . . . . . . . . . . . . . . . . . . . . .  93
4 Page 0x30 Read Sequence   . . . . . . . . . . . . . . . . . . . . . . . .  97
5 PLL Clocking  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
6 Standby Mode and Headset Clamps . . . . . . . . . . . . . . . . . .  97
7 Detection Sequence from Wake  . . . . . . . . . . . . . . . . . . . . .  97
8  VD_FILT/VL ESD Diode . . . . . . . . . . . . . . . . . . . . . . . . . .  101
9 External Output Switch Considerations . . . . . . . . . . . . . . .  101
Register Quick Reference   . . . . . . . . . . . . . . . . . . . . . . . . . . .  102
1 SoundWire Address Maps . . . . . . . . . . . . . . . . . . . . . . . . .  103
2 Slave Control Port Registers  . . . . . . . . . . . . . . . . . . . . . . .  104
3 Slave Data Port 1–3, 15 Registers   . . . . . . . . . . . . . . . . . .  105
4 Global Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  106
5 Power-Down and Headset-Detect Registers . . . . . . . . . . .  107
6 Clocking Registers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  108
7 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  108
8 Fractional-N PLL Registers  . . . . . . . . . . . . . . . . . . . . . . . .  110
9 HP Load Detect Registers . . . . . . . . . . . . . . . . . . . . . . . . .  110
10 Headset Interface Registers  . . . . . . . . . . . . . . . . . . . . . .  110
11 Headset Bias Registers . . . . . . . . . . . . . . . . . . . . . . . . . .  111
12 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  111
13 DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  112
14 HP Control Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
15 Class H Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
16 Mixer Volume Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . 112
17 Equalizer Registers   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
18 AudioPort Interface Registers   . . . . . . . . . . . . . . . . . . . . . 113
19 SRC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
20 DMA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
21 S/PDIF Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
22 Serial Port Transmit Registers  . . . . . . . . . . . . . . . . . . . . . 115
23 Serial Port Receive Registers   . . . . . . . . . . . . . . . . . . . . . 115
24 ID Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
1 SoundWire Control Port 0 Registers   . . . . . . . . . . . . . . . . . 117
2 SoundWire Data Port (1–3) Descriptions  . . . . . . . . . . . . . . 123
3 Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4 Power Down and Headset Detects   . . . . . . . . . . . . . . . . . . 130
5 Clocking Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6 Interrupt Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7 Fractional-N PLL Registers   . . . . . . . . . . . . . . . . . . . . . . . . 146
8 HP Load-Detect Registers  . . . . . . . . . . . . . . . . . . . . . . . . . 148
9 Headset Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . 148
10 Headset Bias Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11 ADC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12 DAC Control Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
13 HP Control Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
14 Class H Register   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
15 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
16 Equalizer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
17 AudioPort Interface Registers   . . . . . . . . . . . . . . . . . . . . . 158
18 SRC Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
19 DMA Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
20 S/PDIF  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
21 Serial Port Register Transmit Registers  . . . . . . . . . . . . . . 162
22 Serial Port Receive Registers   . . . . . . . . . . . . . . . . . . . . . 164
23 ID Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
PCB Layout Considerations  . . . . . . . . . . . . . . . . . . . . . . . . . . 169
1 Power Supply  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
2 Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3 QFN Thermal Pad   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Plots   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
1 Digital Filter Response  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2 Windnoise Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . 176
3 HSBIAS Current Sense vs. VP Voltage per Trip Setting  . . 178
Package Dimensions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
1 WLCSP Package Dimensions  . . . . . . . . . . . . . . . . . . . . . 179
2 QFN Package Dimensions  . . . . . . . . . . . . . . . . . . . . . . . . 180
Thermal Characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Ordering Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
References  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

DS1083F2 3

CS42L42

1 Pin Assignments and Descriptions

This section shows pin assignments and describes pin functions.

1.1 WLCSP Pin Out (Through-Package View)

Figure 1-1. WLCSP Pin Diagram (Through-Package View)

SDA SCL VL ASP_SDOUT ASP_SDIN/

SWIRE_SD

SPDIF_TX VD_FILT

VA AD1 GNDL ASP_SCLK/

SWIRE_CLK

ASP_LRCK/

FSYNC

GNDD INT

FILT+ GNDA AD0 VL_SEL RESET WAKE TSTI

HSIN– TSTI SWIRE_SEL DIGLDO_PDN HPSENSA VCP VP

HSIN+ HS_CLAMP2 HSBIAS_FILT_

REF

TIP_SENSE HPOUTA +VCP_FILT FLYP

HS4 HS_CLAMP1 HSBIAS_

FILT HS4_REF HPSENSB GNDCP FLYC

GNDHS HS3 RING_SENSE HS3_REF HPOUTB –VCP_FILT FLYN

HeadphoneMicrophone Power

Charge

Pump Ground

Digital I/O

DS1083F2 4

CS42L42

1.2 QFN Pin Out (Through-Package View)

Figure 1-2. QFN Pin Diagram

Top- D ow n (Through Package ) View

48 -Pin QFN Package

1413 15 16 17 18 19 20 21 22 23 24

4748 46 45 44 43 42 41 40 39 38 37

SDA

AD0

AD1

FILT+

GNDA

HSIN–

HSIN+

HS4

HS_CLAMP2

HS_CLAMP1

GNDHS

RESET

INT

WAKE

DIGLDO_PDN

TSTI1

VCP

FLYP

FLYC

+VCP_FILT

FLYN

GNDCP

VL_SEL

VD_FILT

GNDD

SPDIF_TX

ASP_SDIN/SWIRE_SD

ASP_LRCK/FSYNC

ASP_SCLK/SWIRE_CLK

ASP_SDOUT

SWIRE_SEL

GNDL

SCL

–VCP_FILT

HPSENSA

HPOUTA

HPOUTB

HPSENSB

TIP_SENSE

HS3_REF

HS4_REF

RING_SENSE

HSBIAS_FILT

HSBIAS_FILT_REF

HS3

–VCP_FILT

HPSENSA

HPOUTA

HPOUTB

HPSENSB

TIP_SENSE

HS3_REF

HS4_REF

RING_SENSE

HSBIAS_FILT

HS3

DS1083F2 5

CS42L42

1.3 Pin Descriptions

Table 1-1. Pin Descriptions

Pin Name CSP

Pin #

QFN

Pin #

Power

Supply I/O Pin Description

Internal

Connection

Driver Receiver State at

Reset

HS_CLAMP1

HS_CLAMP2

VP I

Headset Depletion FET Connections.

Input to drain of

integrated depletion FET for ground-noise rejection.

— — — Input

HS3_REF

HS4_REF

F4 19

20 VP I Headset Connection Reference. Input to

pseudodifferential HP output reference

— — — Input

HS3

HS4

F1 24

28 VP I Headset Connections. Input to headset and

mic-button detection functions

— — — Input

HSBIAS_FILT F3 22 VP I Headset Bias Source Voltage Filter. Filter

connection for the internal quiescent voltage used for

headset bias generation.

— — — Input

HSBIAS_FILT_

REF

E3 23 VP I Headset Bias Source Voltage Filter Reference.

Input of filter connection for the internal quiescent

voltage used for headset-bias generation.

— — — Input

HSIN– D1 30 VP I

Inverting Mic Inputs.

Inverting analog input for the ADC.

— — — Input

HSIN+ E1 29 VP I Noninverting Mic Inputs. Noninverting analog input

for the ADC.

— — — Input

RING_SENSE G3 21 VP I Ring Sense Input. Sense pin to detect S/PDIF or

headphone plug. Can be configured to be debounced

on plug and unplug events independently.

— — — Input

HPOUTA

HPOUTB

16 ±VCP_

FILT

OHeadphone Audio Output. Ground-centered audio

output.

————

HPSENSA

HPSENSB

F5 14

±VCP_

FILT

IHeadphone Audio Sense Input. Audio sense input. — — — Input

TIP_SENSE E4 18 VP I Tip Sense. Output can be set to wake the system.

Independently configurable to be debounced on plug

and unplug events.

—Hi-Z——

AD0

AD1

34 VL I I2C Address Input/SoundWire Instance ID Input.

Address pins for I2C or SoundWire Instance ID [1:0]

input.

— — Hysteresis

on CMOS

input

Input

ASP_LRCK/

FSYNC

B5 43 VL I/O ASP Left/Right Clock or Frame Sync. Left or right

word select, or frame start sync for the ASP interface.

—CMOS

output

Hysteresis

on CMOS

input

Input

ASP_SCLK/

SWIRE_CLK

B4 42 VL I ASP/SoundWire Serial Data Clock. SoundWire

data-shift clock in SoundWire Mode or serial

data-shift clock for the ASP interface in I2S/TDM

Mode. Source clock used for internal master clock

generation.

— — Hysteresis

on CMOS

input

Input

ASP_SDIN/

SWIRE_SD

A5 44 VL I/O ASP Serial Data Input/SoundWire Serial Data

Input and Output. Serial data input and output in

SoundWire mode or serial data input for the ASP

interface in I2S/TDM mode.

—CMOS

output

Hysteresis

on CMOS

input

Input

ASP_SDOUT A4 41 VL O ASP Serial Data Output. Serial data output for the

ASP interface.

Weak

pull-down

CMOS

output

— Output

DIGLDO_PDN D4 4VP I Digital LDO Power Down. Digital core logic LDO

power down.

— — Hysteresis

on CMOS

input

Input

INT B7 2 VP O Interrupt output. Programmable, open-drain,

active-low programmable interrupt output.

—CMOS

open-drain

output

— Output

RESET C5 1 VP I Reset. Hardware reset. — — Hysteresis

on CMOS

input

Input

SCL A2 37 VL I I2C Clock. Clock input for the I2C interface. — — Hysteresis

on CMOS

input

Input

Microphone

Headphone

Digital I/O

DS1083F2 6

CS42L42

1.3 Pin Descriptions

SDA A1 36 VL I/O I2C Input/Output. I2C input and output. — CMOS

open-drain

output

Hysteresis

on CMOS

input

Input

SPDIF_TX A6 45 VL O S/PDIF Audio Serial Data Output. Serial data

output for S/PDIF interface.

—CMOS

output

— Output

SWIRE_SEL D3 40 VL I SoundWire Select. SoundWire interface selection

input. Defines the serial and audio interface type. If

asserted, SoundWire is the control and audio

interface, otherwise I2C is control and TDM/I2S is

used for audio data.

— — Hysteresis

on CMOS

input

Input

VL_SEL C4 48 VP I VL Supply Voltage Select. Select for VL power

supply voltage level. Connect to VP for 1.8-V VL

supply, connect to GNDD for 1.2-V VL supply

— — Hysteresis

on CMOS

input

Input

WAKE C6 3 VP O Wake up. Programmable, open-drain, active-low

output. This outputs the state of the Mic S0 or HP

wake detect.

—Hi-Z,

CMOS

open-drain

output

— Output

–VCP_FILT G6 13 VCP/

VP1

OInverting Charge Pump Filter Connection. Power

supply for the inverting charge pump that provides

the negative rail for the HP amplifier.

————

+VCP_FILT E6 10 VCP/

VP1

OStep Down Charge Pump Filter Connection.

Power supply for the step down charge pump that

provides the positive rail for the HP amplifier.

————

FLYC F7 9VCP/

VP1

OCharge Pump Cap Common Node. Common

positive node for the HP amplifiers’ step-down and

inverting charge pumps’ flying capacitors.

————

FLYN G7 11 VCP/

VP1

OCharge Pump Cap Negative Node. Negative node

for the inverting charge pump’s flying capacitor.

————

FLYP E7 8VCP/

VP1

OCharge Pump Cap Positive Node. Positive node for

HP amps’ step-down charge pump’s flying capacitor.

————

FILT+ C1 32 VA I Positive Voltage Reference. Positive reference

voltage for internal sampling circuits.

————

VA B1 33 N/A I Analog Power Supply. Power supply for the internal

analog section.

————

VCP D6 7N/A I Charge Pump Power. Power supply for the internal

HP amplifiers charge pump.

————

VD_FILT A7 47 N/A I 1.2-V Digital Core Power Supply. Power supply for

internal digital logic.

————

VL A3 39 N/A I I/O Power Supply. Power supply for external

interface and internal digital logic.

————

VP D7 6N/A I High Voltage Interface Supply. Power supply for

high voltage interface.

————

GNDA C2 31 N/A I Analog Ground. Ground reference for the internal

analog section.

————

GNDL B3 38 N/A I Digital Ground. Ground reference for interface

section.

————

GNDHS G1 25 N/A I Headset Ground. Ground reference for the internal

analog section.

————

GNDCP F6 12 N/A I Charge Pump Ground. Ground reference for the

internal HP amplifiers charge pump.

————

GNDD B6 46 N/A I Digital Ground. Ground reference for the internal

digital circuits.

————

TSTI D2, C7 —N/AITest input. Connect to GNDA. — — — —

1.The power supply is determined by ADPTPWR setting (see Section 7.14.1). VP is used if ADPTPWR = 001 (VP_CP Mode) or when necessary for

ADPTPWR = 111 (Adapt-to-Signal Mode).

Table 1-1. Pin Descriptions (Cont.)

Pin Name CSP

Pin #

QFN

Pin #

Power

Supply I/O Pin Description

Internal

Connection

Driver Receiver State at

Reset

Charge Pump

Power

Ground

Test

DS1083F2 7

CS42L42

1.4 Electrostatic Discharge (ESD) Protection Circuitry

Fig. 1-3 provides a composite view of the ESD domains showing the ESD protection paths between each pad and the

substrate (GNDA) and the interrelations between some domains. Note that this figure represents the structure for the

internal protection devices and that additional protections can be implemented as part of the integration into the board.

Figure 1-3. Composite ESD Topology

Table 1-2 shows the individual ESD domains and lists the pins associated with each domain.

ESD-sensitive device. The CS42L42 is manufactured on a CMOS process. Therefore, it is generically

susceptible to damage from excessive static voltages. Proper ESD precautions must be taken while

handling and storing this device. This device is qualified to current JEDEC ESD standards.

Table 1-2. ESD Domains

ESD

Domain

Signal Name (CSP/QFN)

(See * in Topology Figures for Pad) Topology

VL/

GNDA 1

AD0

AD1

ASP_LRCK/FSYNC

GNDL

SCL

SDA

ASP_SDOUT

SPDIF_TX

SWIRE_SEL

ASP_SCLK/SWIRE_CLK

SWIRE_SD/ASP_SDIN

VD_FILT

VD_FILT/

GNDA

VD_FILT

GNDD

TSTI

VA/

GNDA

FILT+

GNDA

GNDL

Substrate

(GNDA)

VA VCP

GNDA

Substrate

(GNDA)

GNDCP

+VCP_FILTVP

–VCP_FILT

GNDHS

____________________

VL/GNDA Domain

____________________

VA/GNDA Domain

__________

VCP/GNDA

Domain

VP/GNDA Domain

_______________

VD_FILT/GNDA

Domain

VP/–VCP_FILT Domain

–VCP_FILT/+VCP_FILT Domain

GNDD

VD_FILT

Note: The asterisks indicate the pads with which the individual

pins from the corresponding domains are associated. These

pins are listed in Table 1-2.

***

GNDL

Substrate

(GNDA)

VD_FILT

Substrate

(GNDA)

GNDD

VD_FILTVL

Substrate

(GNDA)

GNDA

DS1083F2 8

CS42L42

1.4 Electrostatic Discharge (ESD) Protection Circuitry

VCP/

GNDA

VCP

VP/

GNDA

GNDHS

HS3

HS4

HS_CLAMP1

HS_CLAMP2

HSBIAS_FILT

HSBIAS_FILT_REF

HSIN+

HSIN–

VL_SEL

INT

WAKE

RESET

DIGLDO_PDN

+VCP_

FILT/

–VCP_

FILT

+VCP_FILT

–VCP_FILT

FLYN

HPSENSA

HPSENSB

HPOUTA

HPOUTB

GNDCP

VP/

–VCP_

FILT

FLYC

FLYP

HS3_REF

HS4_REF

RING_SENSE

TIP_SENSE

1.See Section 5.8 for additional information regarding VD_FILT andVL.

Table 1-2. ESD Domains (Cont.)

ESD

Domain

Signal Name (CSP/QFN)

(See * in Topology Figures for Pad) Topology

VCP

Substrate

(GNDA)

Substrate

(GNDA)

GNDCP

+VCP_FILTVP

–VCP_FILT

Substrate

(GNDA)

GNDHS

VP/GNDA Domain

VP/–VCP_FILT Domain

+VCP_FILT/–VCP_FILT Domain

DS1083F2 9

CS42L42

2 Typical Connections

Figure 2-1. Typical Connection Diagram for I2C, I2S, or TDM

P_I

P_ I2 C

P_W

Applications

Processor

PMU

2.2 µF

Battery

(3.0–5.0 V)

FLYC

FLYN

2.2 µF

FLYP

2.2 µF

+VCP_FILT

–VCP_FILT

2.2 µF2.2 µF

GNDCP

All external passive component

values shown are nominal.

Key for Capacitor Types Required:

* Use low ESR, X7R/X5R capacitors

If no type symbol is shown next to a

capacitor, any type may be used.

FILT+

10 µF

4.7 µF

HSBIAS_FILT_REF

HSBIAS_FILT

4.7 µF

ASP_LRCK/FSYNC

ASP_SCLK/SWIRE_CLK

SWIRE_SD/ASP_SDIN

ASP_SDOUT

1.8 V

GNDA

SDA

SCL

WAKE

INT

1.8 V/1.2 V

RESET

VCP

VD_FILT

See

DIGLDO_PDN

and VL_SEL

Configurations

DIGLDO_PDN

AD0

GNDL

AD1

2.2 µF

VL_SEL

GNDD

HSIN+

HSIN–

HPOUTB

TIP_SENSE

HPOUTA

HS3

Headset Connector

HS4

Headphone

Output Filter

HS3_REF

HS4_REF

SPDIF_TX

RING_SENSE

GNDHS

HS_CLAMP1

HS_CLAMP2

DIGLDO_PDN and VL_SEL

Configurations

DIGLDO_PDN = 1 (3.0 to 5.0 V)

VD_FILT

DIGLDO_PDN

0.1 µF

1.8 V

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.2 V DIGLDO_PDN

0.1 µF

Opt ical

Transmitter

Module

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.8 V DIGLDO_PDN

0.1 µF

1.2 V

HPSENSB

HPSENSA

SWIRE_SEL

VL_SEL

VL_SEL = 0 (GNDD)

VL_SEL

Battery

(VP = 3.0 to 5.0V)

VL_SEL = 1 (3.0 to 5.0 V)

VL_SEL

Battery

(VP = 3.0 to 5.0V)

VL or VP

Note 3

Note 4

Note 5

Note 6

CS42L42

Note 1

TSTI

DS1083F2 10

CS42L42

2 Typical Connections

Figure 2-2. Typical Connection Diagram for SoundWire

Notes:

1. RP_I and RP_W values can be determined by the INT and WAKE pin specifications in Tabl e 3- 2 5.

2. HPSENSA and HPSENSB are supported only on the WLCSP package.

3. RP_I2C values can be determined by the I2C pull-up resistance specification in Table 3-24.

4. The headphone amplifier’s output power and distortion ratings use the nominal capacitances shown. Larger capacitance reduces ripple on

the internal amplifiers’ supplies and, in turn, reduces distortion at high-output power levels. Smaller capacitance may not reduce ripple

enough to achieve output power and distortion ratings. Because actual values of typical X7R/X5R ceramic capacitors deviate from nominal

values by a percentage specified in the manufacturer’s data sheet, capacitors must be selected for minimum output power and maximum

distortion required. Higher value capacitors than those shown may be used, however lower value capacitors must not (values can vary from

the nominal by ±20%). See Section 2.1.2 for additional details.

5. Series resistance in the path of the power supplies must be avoided. Any voltage drop on VCP directly affects the negative charge-pump

supply (–VCP_FILT) and clips the audio output.

6. Lowering capacitance below the value shown affects PSRR, THD+N performance, ADC–DAC isolation and intermodulation, and

interchannel isolation and intermodulation.

HSIN+

HSIN–

HPOUTB

TIP_SENSE

HPOUTA

HS3

Headset Connector

HS4

Headphone

Output Filt er

HS3_REF

HS4_REF

SPDIF_TX

RING_SENSE

Optical

Transmitter

Module

DIGLDO_PDN and VL_SEL

Configurations

DIGLDO_PDN = 1 (3.0 to 5.0 V)

VD_FILT

DIGLDO_PDN

0.1 µF

1.8 V

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.2 V DIGLDO_PDN

0.1 µF

DIGLDO_PDN = 0 (GNDD)

VD_FILT

1 µF

1.8 V DIGLDO_PDN

0.1 µF

1.2 V

VL_SEL

VL_SEL = 0 (GNDD)

VL_SEL

Battery

(VP = 3.0 to 5.0V)

VL_SEL = 1 (3.0 to 5.0 V)

VL_SEL

Battery

(VP = 3.0 to 5.0V)

GNDHS

FLYC

FLYN

2.2 µF

FLYP

2.2 µF

+VCP_FILT

–VCP_FILT

2.2 µF2.2 µF

GNDCP

FILT+

10 µF

4.7 µF

HSBIAS_FILT_REF

HSBIAS_FILT

4.7 µF

GNDA

SDA

SCL

_____

WAKE

RESET

VCP

2.2 µF

All external passive component

values shown are nominal.

Key for Capacitor Types Required:

* Use low ESR, X7R/X5R capacitors

If no type symbol is shown next to a

capacitor, any type may be used.

2.2 µF

VD_FILT

See

DIGLDO_PDN

and VL_SEL

Configurations

DIGLDO_PDN

VL_SEL

ASP_LRCK/FSYNC

ASP_SCLK/SWIRE_CLK

SWIRE_SD/ASP_SDIN

ASP_SDOUT

AD0

GNDL

AD1

GNDD

SWIRE_SEL

P_W

PMU

Battery

(3.0–5.0 V) 1.8 V 1.8 V/1.2 V VL or VP

P_I

Applications

Processor

INT

VL or VP

Optional Connections

Note 1

Note 5

Note 4

Note 6

CS42L42

Note 1

TSTI

Table des matières

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