DATA BLOCK
The data block contains the data Bark,
data field and the EDC- bytes.
the
the data block starting with the Data- AM and
ending with the last byte of the data field
through a16- bit shift register described by
the following generator polinomial:
16 12 _. 5
DATA MARK
This field comprises 7bytes (see Fig. 1-6).
The 6bytes of zeros in front of the data ad-
dress -ark are for synchronisation of the da-
ta separator circuit in the host system. The
data address mark byte contains FB in front
of anormal data field. When adeleted data
field follows, F8 must be written. The clock
pattern of the data address mark is C7 (C6,
CS and C4 missing).
DATA FIELD
This field comprises 128 bytes .If it comprises
less than 128 bytes, the remaining positions
shall be filled with zeroes.
EDC -BYTES
These two bytes are hardware generated by the
host system by shifting serially the bits of
EDC- IMPLEMENTATION
Fig. 1-7 is asimplified logic of ashift re-
gister, which may be used to generates the
EDC bytes.
Prior to the operation, all positions of the
shift register are set to ONE. Input data are
added (exclusive OR) to the contents of po-
sition C15 of the register to form afeed-
back .This feedback is in its turn added
(exclusive OR) to the contents of position C4
and position Cn .
On shifting, the outputs of the exclusive OR
gates are entered respectively into positions
Co, C5and Ci 2.After the last data pit has
been added, the register is shifted once more
as specified above.
The register then contains the EDC bytes. If
further shifting is to take place during the
writing of the EDC bytes, the control signal
inhibits exclusive OR operations.
To check for errors when reading, the data bits
are added into the shift register in exactly
the same manner as they were during writing.
After the data the EDC bytes are also entered
into the shift register as if they were data.
After the final shift, the register contents
will be all 2ER0 if the record does not con-
tain errors.
CONTROL
JcX^--^ JD^
L-IHPOT
OUTPUT
for EDC
writing
-FIGURE 1-7.SIMPLIFIED EDC SHIFT REGISTER
