Atari 400 Manuel utilisateur

ATARI®

PERSONAL

COMPUTER

SYSTEM

•

HARDWARE

MANUAL

ATAR

I®

A Warner Communications Company

~

Every

effort

has been

made

to

ensure

that

this

manual

is

an

accurate

document. However, due

to

the

ongoing improvement

and update

of

the

computer software and hardware,

ATARI,

INC.

cannot guarantee

the

accuracy

of

printed

material

after

the

date

of

publication,

nor can

ATARI,

INC.

accept

responsibility

for

errors

or

omissions.

I.

II.

III.

IV.

v.

VI.

TABLE

OF

CONTENTS

INTRODUCTION.

• •• • ••• •• •• • •• •• • •• •• •• •• • ••. • • •

I.

1

DESCRIPTION

OF

HARDWARE

••••••••••••••••••••••

II.1

A.

ANTIC

and

CTIA

•••••••••

••••••••••••••

•••

II.1

B.

POKEY

••••••••••••••••••••••••••••••

•••••

11.23

C.

SERIAL

PORT

•••••••••••••••••••••••••••••

II.25

D.

INTERRUPT

SYSTEM

••••••••••••••••••••••••

II.28

E.

CONTROLLERS

•••••••••••••••••••••••••••••

II.30

HARDWARE

REGISTERS

••••••••••••••••••••••••••

III

.1

A.

PAL••••••••••••••••••••••••••••••••••••III.l

B.

INTERRUPT

CONTROL

••••••••••••••••••••••

III.1

C.

TV

LINE

CONTROL

••••••••••••••••••••••••

III.3

D.

GRAPHICS

CONTROL

••••••••••••••

•••••••••

III.4

E.

PLAYERS

AND

MISSILES

•••••••••••••••••••

III.9

F.

AUDIO

•

•••••••••••••••••••••••••••••••••

I I

I.

12

G.

KEYBOARD

and

SPEAKER

•••••••••••••••••••

III.15

H.

SERIAL

PORT••••••••••••••••••••••••••••III.17

I.

CONTROLLER

PORTS

•••••••••••••••••••••••

III.19

SAMPLE

DISPLAY

PROGRAM

•••••••••••••••••••••••

IV.1

HARDWARE

REGISTER

LISTS

•••••••••••••••••••••••

V.1

A.

ADDRESS

ORDER.

•••••••••••••••••••••••••••V.1

B.

ALPHABETICAL

ORDER

•••••••••••••••••••••••

V.S

FIGURES

•

•••••••••••••••••••••••••••••••••••••

VI.

1

A.

11EMORY

MAP

•

•••••••••••••••••••••••••••••

VI.

1

B.

NTSC

and

PAL

DISPLAY

••••••••••••••••••••

VI.2

C.

SCHEMATICS

•

••••••••••••••••••••••••

••••

•

VI.

3

APPENDIX

A:

APPENDIX

B:

APPENDIX

C

USE

OF

PLAYER/MISSILE

GRAPHICS

WITH

BASIC

MIXING GRAPHICS

MODES

PINOUTS

ii

l·

INTRODUCTION

The

ATARI

(R)

800™

and

ATARI

400™

Personal

Computer

Systems

contain

a 6502

microprocessor,

4

I/O

chips,

operating

system

ROM,

expandable

RAM,

and

several

MSI

chips

for

address

decoding

and

data

bus

buffering.

This

manual

is

primarily

intended

to

describe

the

4

I/O

chips

in

sufficent

detail

to

allow

experienced

programmers

to

create

assembly

language

programs,

such

as

video

games.

All

four

Input/Output

chips

are

controlled

by

the

microprocessor

by

writing

directly

into

their

registers

which

are

decoded

to

exist

in

microprocessor

memory

space

just

as

RAM

does.

These

I/O

chips

can

also

be

interrogated

by

the

microprocessor

by

reading

similar

registers.

Many

registers

are

write

only

and

cannot

be

read

after

they

are

written.

In

some

cases,

reading

from

the

same

address

gives

the

value

contained

in

a

separate

read

only

register.

Some

write

only

registers

are

strobes.

No

data

bits

are

needed

in

this

case

since

the

presence

of

the

address

on

the

bus

is

what

triggers

the

requested

action.

The

usual

convention

is

to

use

the

STA

(Store

Accumulator)

instruction

for

such

registers.

For

example,

STA

WSYNC

performs

the

wait

for

Sync

function.

STX

(Store

X)

or

STY

(Store

Y)

would

work

just

as

well.

In

BASIC, a

POKE

could

be

used

(the

data

could

be

anything).

Reading

a

register

is

accomp-

lished

by

using

any

of

the

load

instructions

(LDA,

LDX

etc.).

In

BASIC

a

PEEK

would

be

used.

When

the

hardware

register

names

are

defined

in

an

equate

list,

the

programmer

can

refer

to

the

registers

by

name

rather

than

using

the

addresses

directly.

It

is

really

not

necessary

for

the

programmer

to

know

which

I/O

functions

are

performed

by

which

of

the

4

chips,

however

it

does

help

in

learning

these

functions.

This

manual

should

be

used

in

conjunction

with

the

Operating

System

(OS)

Manual,

a 6502

programming

manual,

and

the

ATARI

400/800

Basic

Reference

Manual.

CHIP

NAME

ANTIC

CTIA

FUNCTION

DMA(Direct Memory

Access)

control

NMI(Non-Maskable

Interrupt)

control

Vertical

and

Horizontal

fine

scrolling

Light

pen

position

registers

Vertical

line

counter

WSYNC(wait

for

horizontal

sync)

Priority

control

(display

of

overlapping

objects)

Color-Lumimance

control

(colors

and

brightness

assigned

to

all

objects

including

DMA

objects

from

ANTIC

)

PLAYER-MISSILE

objects

(4

players

and 4

missiles)

Graphics

registers

Size

control

Horizontal

position

control

Collision

detection

between

all

objects

Switches

and

triggers

(miscellaneous

I/O

functions)

I.l

CHIP

NAME

POKEY

PIA

FUNCTION

Keyboard

scan

and

control

Serial

communications

port

(bidirecti

mal)

Pot

scan

(digitizes

position

of

8

indepen~~

n

t

pots)

Audio

generation

(4

channels)

Timers

IRQ

(maskable

interrupt)

control

from

peripher?

: s

Random number

generator

Controller

(Joystick)

jacks

read

or

write

Peripheral

control

and

interrupt

lines

IRQ

(maskable)

interrupt

control

from

peripherals

Section

II

describes

the

hardware

in

some

detail,

including

the

various

graphics

modes.

Section

III

lists

the

hardware

registers

one

at

a

time,

describing

what

each

bit

is

used

for.

It

is

organized

by

functional

groups

(interrupts,

graphics,

audio,

etc.).

Section

IV

contains

a

sample

display

program.

Section

V

contains

various

figures

and

block

diagrams

of

the

system.

Sections

VI

and

VII

list

the

hardware

registers

in

address

order

and

alphabetical

order.

Section

VII

includes

hex

and

decimal

addresses,

the

OS

shadow

registers

and

the

page

numbers

where

more

infor-

mation

can

be

found.

1.2

II.

DESCRIPTION

OF

HARDWARE

A.

ANTIC

AND

CTIA

TV

Display:

The

ANTIC

and

CTIA

chips

generate

the

television

display

at

the

rate

of

60

frames

per

second

on

the

NTSC

(US)

system.

The

PAL

(European)

system

is

different

and

is

described

in

the

section

on

NTSC

vs

PAL.

Each

frame

consists

of

262

horizontal

TV

lines

and

each

line

is

made up

of

228

color

clocks,

as

shown

in

figure

VI-3.

The 6502

microprocessor

runs

at

1.79

MHz.

This

rate

was

chosen

so

that

one

machine

cycle

is

equivalent

in

length

to

two

color

clocks.

One

clock

is

approximately

equal

in

width

to

two

TV

lines.

In

any

graphics

mode,

the

display

is

divided

up

into

small

squares

or

rectangles

called

pixels

(picture

elements).

The

highest

resolution

graphics

mode

has

a

pixel

size

of

1/2

color

clock

by

1

TV

line.

A

sample

display

list

is

given

in

section

IV.

The

current

TV

line

may

be

determined

by

reading

the

vertical

counter

(VCOUNT).

This

register

gives

the

line

count

divided

by

2.

There

are

262

lines

per

frame

so

VCOUNT

runs

from 0

to

130 (0

to

155 on

the

PAL

system).

The 0

point

occurs

near

the

end

of

vertical

blank

(see

figure

VI.5).

Vertical

blank

(VBLANK)

is

the

time

during

which

the

electron

beam

returns

back

to

the

top

of

the

screen

in

preparation

for

the

The

Atari

800

does

not

do

interlacing,

so

each

frame

is

identical

unless

the

program

which

is

being

executed

changes

the

display.

Vertical

sync

(VSYNC)

occurs

during

the

fourth

through

sixth

lines

of

vertical

blank

(VCOUNT

•

hex

7D

through

7F).

This

tells

the

TV

set

where

each

frame

starts.

After

VSYNC,

there

are

16 more

lines

of

VBLANK

for

a

total

of

22

lines

of

VBLANK.

The

display

list

jump and

wait

instruction

(to

be

described

later)

causes

the

display

list

graphics

to

start

at

the

end

of

VB

LANK.

Operating

System

(OS): The

ATARI

400/800

comes

with

a

lOK

Operating

System

(OS)

in

ROM.

The

OS

affects

some

of

the

hardware

registers,

so

it

will

be

mentioned

from

time

to

time

in

this

manual.

Refer

to

the

OS

manual

for

more

details.

The

OS

descriptions

in

this

manual

apply

to

the

version

that

was

being

distributed

when

this

manual

was

written.

The

OS

supports

most

of

the

hardware

graphics

modes (BASICS,

GRAPHICS,

PLOT,

and

DRAWTO

commands). The

OS

always

displays

24

background

lines

after

the

end

of

vertical

blank.

This

convention

is

used

at

Atari

to

compensate

for

television

sets

which

overscan.

Most

TV's

are

designed

so

that

the

edges

of

the

picture

are

cut

off.

This

is

fine

for

ordinary

broadcasts,

but

with

a

computer

it

is

essential

for

all

important

information

to

be

displayed

on

the

screen.

It

is

fairly

common

for

four

to

eight

color

clocks

at

the

right

or

left

edge

of

the

picture

to

overscan.

A

TV

set

that

has

excessive

overscan

may

have

to

readjusted

to

obtain

a

satisfactory

display.

II.1

The

OS

uses

192

TV

lines

for

its

display

and

devotes

the

remaining

24

lines

to

overscan.

It

uses

the

standard

display

width

of

160

color

clocks.

The

hardware

will

allow

displays

of

any

length,

but

it

is

recom-

mended

that

the

standards

be

follo~ed.

The

exception

might

be

a

border

or

other

information

which

is

merely

decorative

and

not

essential

to

use

of

the

program.

OS

Shadowing:

Since

many

of

the

hardware

registers

are

write-only

and

cannot

be

read

the

OS

has

a number

of

"shadow

registers"

in

RAM.

Every

TV

frame

during

vertical

blank

the

OS

takes

the

values

in

some

of

its

shadow

registers,

and

writes

them

out

to

the

corresponding

hardware

register.

The

OS

does

attract

color

shifting

on

all

of

the

color

registers

if

ATRACT

(on

OS

register)

is

negative.

This

is

to

prevent

damage

to

the

TV

screen

phosphors

which

can

occur

if

the

brightness

is

turned

up

too

high

and

the

same

high-luminance

display

is

left

on

for

a

long

time.

The

OS

also

reads

the

joysticks

and

other

controllers

during

vertical

blank

and

stores

the

results

in

shadow

registers,

so

that

user

programs

do

not

have

to

include

code

to

unpack

the

data.

There

are

a few

interrupt-related

registers

which

the

OS

changes

or

reads

during

interrupt

processing.

Programs

usually

access

the

OS

shadow

registers

instead

of

accessing

the

hardware

directly.

However,

the

OS

shadowing

can

be

disabled

by

changing

the

vertical

blank

and

interrupt

vectors

(see

OS

manual).

WSYNC:

In

addition

to

a

Vertical

Blank

Interrupt,

which

allows

the

Microprocessor

to

synchronize

to

the

vertical

TV

display,

this

system

also

provides

a

Wait

for

Horizontal

Sync

(WSYNC)

command

that

allows

the

microprocessor

to

synchronize

itself

to

the

TV

horizontal

line

rate.

This

sync

takes

effect

when

the

processor

writes

to

an

I/O

location

called

WSYNC,

whenever

it

desires

horizontal

synchronization.

Writing

to

this

address

sets

a

latch

which

pulls

to

zero

a

on

the

microprocessor

called

READY.

When

READY

goes

to

zero

the

microprocessor

stops

and

waits.

The

latch

is

automatically

reset

(returning

READY

true)

at

the

beginning

of

the

blank

interval,

releasing

the

microprocessor

to

resume

program

execution.

Object

DMA

(Direct

Memory

Access):

The

primary

function

of

the

Antic

chip

is

to

fetch

data

from

memory

(independent

of

the

microprocessor)

for

display

on

the

TV

screen.

It

does

this

with

a

technique

called

"Direct

Memory

Access"

or

DMA.

It

requests

the

use

of

the

memory

address

and

data

bus

by

sending

a

signal

called

HALT

to

the

microprocessor,

causing

the

processor

to

become "TRI-STATE"

(open

circuit)

all

during

the

cycle.

The

ANTIC

chip

then

takes

over

the

address

bus

and

reads

any

data

it

wishes

from

memory.

Another

name

for

this

type

of

DMA

is

"cycle

stealing".

Once

initiated,

this

DMA

is

completely

and

automatically

controlled

by

the

Antic

chip

without

need

for

futher

microprocessor

intervention.

There

are

two

types

of

DMA:

Playfield

and

Player-Missile

(see

Figure

II.2).

The

playfield

DMA

control

circuit

on

the

Antic

chip

resembles

a

small

dumb

microprocessor.

By

halting

the

main

microprocessor

it

can

fetch

its

own

instructions

from

memory

(the

display

list)

addressed

by

its

program

counter(display

list

pointer).

Each

instruction

defines

the

type

(alpha

character

or

memory

map),

and

the

resolution

(size

of

bits

on

the

screen),

and

the

location

of

the

data

in

memory

which

is

to

be

displayed

on

the

of

lines.

II.

2

In

order

to

begin

this

DMA

the

main

microprocessor

must

store

a

display

list

of

instructions

in

memory,

store

data

to

be

displayed

in

memory,

tell

the

ANTIC

where

the

display

list

is

(initialize

the

display

list

point'er)

and

enable

the

DMA

control

flags

on

the

ANTIC

(DMACTL

register).

In

addition

to

the

playfield

DMA

described

above,

the

ANTIC

chip

simultaneously

controls

another

DMA

channel.

This

type

of

DMA

addresses

PLAYER-MISSILE

graphics

data

stored

in

memory

and

passes

the

graphics

data

on

to

the

CTIA

chip

graphics

registers.

This

type

of

DMA

(if

enabled)

occurs

automatically,

interspersed

with

the

playfield

DMA

described

previously.

This

PLAYER-MISSILE

DMA

has

no

display

list

or

instructions,

and

is

therefore

much

simpler

than

the

PLAYFIELD

DMA.

In

addition

to

the

two

types

of

display

DMA,

the

ANTIC

chip

also

generates

DMA

addresses

for

the

refresh

of

the

dynamic

memory

RAM

used

in

this

system.

This

is

also

completely

automatic

and

need

be

consider-

ed

by

the

programmer

only

if

he

is

concerned

with

real-time

programming

where

an

exact

count

of

the

computer

cycles

is

important.

Color-luminance:

A

color-luminance

register

is

used

on

the

CTIA

chip

for

each

Player-Missile

and

Playfield

type.

Each

color-lum

register

is

loaded

by

the

microprocessor

with

a

code

representing

the

desired

color

and

luminance

of

its

corresponding

Player-Missile

or

Playfield

type.

As

the

serial

data

passes

through

the

CTIA

chip

it

is

"impressed"

with

the

color

and

luminance

values

contained

in

these

registers,

before

being

sent

to

the

TV

display.

In

areas

of

the

screen

where

there

are

no

objects

the

background

color

(COLBK)

is

displayed.

The

CTIA

also

does

collision

detection

(to

be

described

later).

Priority:

When

moving

objects,

such

as

players

and

missiles,

overlap

on

the

TV

screen

(with

each

other

or

with

Playfield)

a

decision

must

be

made

as

to

which

object

shows

in

front

of

the

other.

Objects

which

appear

to

pass

in

front

of

other

·s

are

said

to

have

Priority

over

them.

Priority

is

assigned

to

all

objects

by

the

CTIA

chip

before

the

serial

data

from

each

object

is

combined

with

the

other

objects

and

sent

to

the

TV

screen.

The

priority

of

objects

can

be

controlled

by

the

microprocessor

by

writing

into

the

control

register

PRIOR. The

functions

of

the

bits

in

this

register

are

given

in

the

table

in

the

PRIOR

register

description

in

section

III.

Players

and

Missiles:

The

players

and

missiles

are

small

objects

which

can

be

moved

quickly

in

the

horizontal

direction

by

changing

their

position

registers.

They

are

called

players

and

missiles

because

they

were

originally

designed

to

be

used

in

games

for

objects

such

as

airplanes

and

bullets.

However,

there

are

many

other

possible

applications

for

them.

The

four

player-missile

color

registers,

in

conjunction

with

the

four

playfield

color

registers

and

the

background

color

register,

make

it

possible

to

display

9

different

colors

at

the

same

time.

II.3

MICRO

PROCESSOR

Fi

gure

II.

2

OBJECTS

(no

objects

background)

,..------It

f.....__

_

___,

l

MEMORY

MAP

CHARACTERS

-----

_-

__

,.

"'Player

Missile

DMA

Enable

MEMORY

---

0 B J E C T D I S P L A Y

II.

4

controlled

by

Display

list

instructions

~

:J·f

- - -

-0

(DMACTL)

'

Playfield

DMA

Enable

S 0 U R C E S

There

are

a

total

of

four

players

and

four

missiles.

The

four

missiles

may

be

grouped

together

and

used

as

a

5th

player.

These

objects

are

positioned

horizontally

by

8

horizontal

position

registers

(HPOS

(X)).

These

registers

may

be

reloaded

at

any

time

by

the

proces-

sor,

allowing

an

object

to

be

replicated

many

times

across

a

horizontal

TV

line.

The

shape

of

a

player-missile

is

determined

by

the

data

in

its

graphics

register

(GRAF

(X)).

Players

have

independent

8

bit

graphics

registers.

The

four

missiles

have

2

bit

registers

(located

within

one

address).

These

registers

may

also

be

reloaded

at

any

time

by

the

processor,

although

they

are

usually

changed

during

horizontal

blank

time.

The

data

in

each

graphics

register

is

placed

on

the

display

whenever

the

horizontal

sync

counter

equals

the

corresponding

horizon-

tal

position

register.

The same

data

will

be

displayed

every

line

unless

the

graphic

registers

are

reloaded

with

new

data.

The

player-missile

graphic

registers

may

be

reloaded

by

the

micro-

processor

(GRAF

(X)),

or

automatically

from

memory

with

direct

memory

access

(DMA)

(see

figure

II.3).

The

programmer

must

place

the

object

graphics

in

memory,

write

the

player-missile

base

address

(PMBASE),

and

enable

player-missile

DMA

(DMACTL,

GRACTL).

The

transfer

of

object

graphics

from

memory

to

display

is

then

fully

automatic.

PMBASE

specifies

the

most

significant

byte

(MSB)

of

the

address

of

the

player-missile

graphics.

The

location

of

the

graphics

for

each

object

is

determined

by

adding

an

offset

to

PMBASE

*256

(decimal).

The

bytes

between

the

base

address

and

the

missile

data

are

not

used

by

Antic,

so

they

are

available

to

the

programmer.

Only

the

five

most

significant

bits

of

PMBASE

are

used

with

single-line

resolution

and

the

six

most

significant

bits

are

used

with

two-line

resolution.

This

means

that

the

location

of

the

graphics

in

memory

is

restricted

to

certain

page

boundaries.

Two-line

resolu-

tion

means

that

each

byte

of

data

is

repeated

for

two

lines.

(see

DMACTL,

bit

4).

640

(decimal)

bytes

(5X128)

are

required

for

two-line

resolution

and

1280

bytes

(Sx256)

for

one-line

resolution.

Each

byte

in

the

player

graphics

area

represents

eight

pixels

which

are

to

be

displayed

on

the

corresponding

line(s)

of

the

TV

screen.

A

1

indicates

that

the

player's

color-lum

is

to

be

displayed

in

that

pixel.

The

graphics

may

be

anything,

not

just

rectangles

like

the

ones

in

figure

II.3.

The

player

graphics

may

fill

the

entire

height

of

the

screen

or

they

may

be

only

a

couple

of

lines

high

if

the

rest

of

the

display

data

is

all

O's.

Each

byte

in

the

mis$ile

display

also

r

epresents

eight

pixels,

two

pixels

for

each

missile.

Each

pixel

may

be

1,

2,

or

4

color

clocks,

and

is

determined

by

the

SIZE

registers.

Plavfield:

Playfield

is

always

generated

by

DMA.

There

are

four

playfields,

each

identified

by

its

own

color-lum

register

and

collision

detection.

Playfield

is

generated

by

two

different

DMA

techniques:

memory

map

and

character.

Both

methods

provide

lists

of

instructions

in

memory,

independent

of

the

player-missile

generation.

rr.s

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