ARM Corstone SSE-300 Manuel utilisateur

Arm® Corstone™ SSE-300 with Cortex®-M55

and Ethos™-U55 : Example Subsystem for MPS3

Revision: C

Application Note AN547

Non-Confidential

Issue C

DAI 0547C

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

Non-Confidential

Page 2 of 64

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Example

Subsystem for MPS3

Application Note AN547

Release information

Document history

Issue

Date

Confidentiality

Change

30 November 2020

Confidential

First Issue

29 January 2021

Non-Confidential

Confidentiality status changed to Non-Confidential

30 June 2021

Non-Confidential

Document title change,

Added selftest support for DS 2020.1

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the

information contained in this document may be protected by one or more patents or pending patent

applications. No part of this document may be reproduced in any form by any means without the express prior

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rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or

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third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES,

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This document may include technical inaccuracies or typographical errors.

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Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

Non-Confidential

Page 3 of 64

The Arm corporate logo and words marked with ®or ™ are registered trademarks or trademarks of Arm Limited

document may be the trademarks of their respective owners. Please follow Arm's trademark usage guidelines at

http://www.arm.com/company/policies/trademarks.

Arm Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

(LES-PRE-20349)

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license

restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm

delivered this document to.

Unrestricted Access is an Arm internal classification.

Product Status

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Web Address

developer.arm.com

Progressive terminology commitment

Arm values inclusive communities. Arm recognizes that we and our industry have used terms that can be

offensive. Arm strives to lead the industry and create change.

This document includes terms that can be offensive. We will replace these terms in a future issue of this

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Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

Non-Confidential

Page 4 of 64

LICENCE GRANTS

THE END USER LICENCE AGREEMENT FOR THE ARM SYSTEM OR SUBSYSTEM FOR AN ARM FPGA

PROTOTYPING BOARD (“THE LICENCE”), LES-PRE-21902, DEFINES THE LICENCE GRANTS.

DELIVERABLES

Part A

Hardware Binaries:

Encrypted FPGA bitstream file containing various the Arm technology including:

SSE-300 Subsystem

Cortex-M55 Processor

Ethos-U55 Embedded ML Inference processor.

Software Binaries:

Motherboard Configuration Controller binary (mbb_vxxx.ebf), including Keil®USB and SD card drivers, and

Analog Devices FMC EEPROM reader.

selftest binary (an547_st.axf) for Cortex-M55 in Corstone™ SSE-300.

Documentation:

Documentation, provided as PDF

Part B

Text configuration files (.txt) in the <install_dir>/Boardfiles/MB/HBI0309x/ directory:

/board.txt

/AN547/an547_vx.txt

/AN547/images.txt

Part C

None

Part D

None

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : 
Example Subsystem for MPS3 - Application Note AN547 
DAI 0547C 
Issue C 
 
 
Copyright ©2020, 2021 Arm Limited (or its affiliates). All rights reserved. 
Non-Confidential 
 Page 5 of 64 
Contents 
Introduction........................................................................................................................................................... 8 
1 Intended audience.................................................................................................................................................... 8 
2 Conventions ............................................................................................................................................................... 8 
2.1 Glossary.................................................................................................................................................................... 8 
2.2 Typographical conventions ............................................................................................................................... 9 
3 Additional reading.................................................................................................................................................... 9 
4 Feedback....................................................................................................................................................................10 
4.1 Feedback on this product.................................................................................................................................10 
4.2 Feedback on content .........................................................................................................................................10 
4.3 Other information ..............................................................................................................................................11 
Preface ..................................................................................................................................................................12 
1 Purpose of this application note........................................................................................................................12 
2 Terms and abbreviations .....................................................................................................................................12 
3 Arm IP version details ...........................................................................................................................................13 
4 Encryption key.........................................................................................................................................................13 
Overview ..............................................................................................................................................................14 
1 System block diagram ...........................................................................................................................................14 
2 SSE-300 Configuration.........................................................................................................................................15 
2.1 Render Settings ...................................................................................................................................................15 
2.2 Subsystem static input values.........................................................................................................................17 
3 SIE-300 Components............................................................................................................................................18 
4 SIE-200 Components............................................................................................................................................18 
5 CoreLink XHB-500.................................................................................................................................................18 
6 Memory Protection ...............................................................................................................................................18 
7 Memory Map Overview .......................................................................................................................................19 
8 Expansion System peripherals...........................................................................................................................22 
8.1 Manager Peripheral Expansion Low Latency Interface Memory Map (HMSTEXPPILL)...........22 
8.2 MSTEXPPIHL Peripheral Map........................................................................................................................25 
9 FPGA Utilization.....................................................................................................................................................27 
9.1 Total design utilization......................................................................................................................................27 
Programmers Model .........................................................................................................................................28 

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : 
Example Subsystem for MPS3 - Application Note AN547 
DAI 0547C 
Issue C 
 
 
Copyright ©2020, 2021 Arm Limited (or its affiliates). All rights reserved. 
 Non-Confidential 
Page 6 of 64 
1 ITCM ...........................................................................................................................................................................28 
2 FPGA SRAM .............................................................................................................................................................28 
3 DTCM .........................................................................................................................................................................28 
4 QSPI.............................................................................................................................................................................28 
5 DDR4 ..........................................................................................................................................................................28 
6 AHB GPIO .................................................................................................................................................................29 
7 SPI ................................................................................................................................................................................29 
8 SBCon (I2C) ...............................................................................................................................................................29 
9 UART...........................................................................................................................................................................30 
10 Color LCD parallel interface ............................................................................................................................30 
11 Ethernet ..................................................................................................................................................................31 
12 USB............................................................................................................................................................................31 
13 RTC ...........................................................................................................................................................................31 
14 Audio I2S..................................................................................................................................................................32 
15 Audio Configuration ...........................................................................................................................................33 
16 FPGA system control and I/O..........................................................................................................................34 
17 Serial Configuration Controller (SCC)..........................................................................................................35 
Clock architecture .............................................................................................................................................37 
1 Clocks..........................................................................................................................................................................37 
1.1 Source clocks........................................................................................................................................................37 
1.2 Generated clocks ................................................................................................................................................37 
1.3 SSE-300 clocks.....................................................................................................................................................38 
FPGA Secure Privilege Control......................................................................................................................39 
Interrupt Map......................................................................................................................................................43 
1 UART Interrupts .....................................................................................................................................................45 
Shield Support.....................................................................................................................................................46 
ZIP Bundle Description ....................................................................................................................................48 
1 Overall Structure....................................................................................................................................................48 
2 Bundle Directory Tree/Structure .....................................................................................................................48 
Board Revision And Support........................................................................................................................50 
1 Identifying the MPS3 board revision ............................................................................................................50 
2 Bundle support for specific MPS3 board revisions..................................................................................50 

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

Non-Confidential

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11 Using AN547 on the MPS3 Board...............................................................................................................51

11.1 Pre-Requisites.......................................................................................................................................................51

11.2 Loading a prebuilt image onto the MPS3 Board........................................................................................51

11.3 UART Serial Ports ................................................................................................................................................52

11.4 UART Serial Port Terminal Emulator Settings...........................................................................................52

11.5 MPS3 USB Serial port drivers for Windows...............................................................................................52

11.6 MCC Memory mapping......................................................................................................................................53

12 Software.............................................................................................................................................................54

12.1 Rebuilding software............................................................................................................................................54

12.2 Loading software on the MPS3 board ..........................................................................................................54

13 Debug..................................................................................................................................................................55

13.1 Debug Connectivity ............................................................................................................................................55

13.2 Debug support for Keil MDK...........................................................................................................................55

13.3 Trace support for Keil MDK.............................................................................................................................57

13.4 Debug and Trace support for Arm Development Studio .......................................................................58

13.4.1 Establishing a Debug Session.......................................................................................................................58

13.4.2 Trace in Debug session...................................................................................................................................62

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

1 Introduction

Non-Confidential

Page 8 of 64

1Introduction

1.1 Intended audience

This application note document is written for experienced hardware, System-on-Chip (SoC) and

software engineers who might or might not have experience with Arm products. Such engineers

typically have experience in writing Verilog and of performing synthesis but might have limited

experience of integrating and implementing Arm products.

1.2 Conventions

The following subsections describe conventions used in Arm documents.

1.2.1 Glossary

The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those

terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning

differs from the generally accepted meaning.

See the Arm Glossary for more information: https://developer.arm.com/glossary.

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

1 Introduction

Non-Confidential

Page 9 of 64

1.2.2 Typographical conventions

Convention

Use

italic

Introduces citations.

bold

Highlights interface elements, such as menu names. Denotes signal names. Also used for

terms in descriptive lists, where appropriate.

monospace

Denotes text that you can enter at the keyboard, such as commands, file and program

names, and source code.

monospace bold

Denotes language keywords when used outside example code.

monospace

underline

Denotes a permitted abbreviation for a command or option. You can enter the underlined

text instead of the full command or option name.

<and>

Encloses replaceable terms for assembler syntax where they appear in code or code

fragments.

For example:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in

the Arm®Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC,

UNKNOWN, and UNPREDICTABLE.

This represents a recommendation which, if not followed, might lead to system failure or

damage.

This represents a requirement for the system that, if not followed, might result in system

failure or damage.

This represents a requirement for the system that, if not followed, will result in system

failure or damage.

This represents an important piece of information that needs your attention.

This represents a useful tip that might make it easier, better or faster to perform a task.

This is a reminder of something important that relates to the information you are reading.

1.3 Additional reading

This document contains information that is specific to this product. See the following documents for

other relevant information:

Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 :

Example Subsystem for MPS3 - Application Note AN547

DAI 0547C

Issue C

1 Introduction

Non-Confidential

Page 10 of 64

Document name

Document ID

Licensee only

Arm® MPS3 FPGA Prototyping Board Technical

Reference Manual

100765

Arm® Corstone™ SSE-300 Example Subsystem

Technical Reference Manual

101773

Arm® Corstone™ SSE-300 Example Subsystem

Configuration and Integration Manual

101774

Yes

Arm® Ethos™-U55 NPU Technical reference manual

101885

Arm® CoreLink™ SIE-200 System IP for Embedded

Technical Reference Manual

DDI 0571

Arm® CoreLink™ SIE-300 AXI5 System IP for

Embedded Technical Reference Manual

101526

Arm® Cortex®-M System Design Kit Technical

Reference Manual

DDI 0479

Arm® CoreLink™ XHB-500 Bridge Technical

Reference Manual

101375

MCBQVGA-TS-Display-v12 –Keil MCBSTM32F200

display board schematic

Arm® MPS3 FPGA Prototyping Board Getting

Started Guide

Table 1-1 : Arm Publications

1.4 Feedback

Arm welcomes feedback on this product and its documentation.

1.4.1 Feedback on this product

If you have any comments or suggestions about this product, contact your supplier and give:

•The product name.

•The product revision or version.

•An explanation with as much information as you can provide. Include symptoms and diagnostic

procedures if appropriate.

1.4.2 Feedback on content

If you have comments on content, send an email to [email protected]om and give:

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