ALPHI TECHNOLOGY PCI-ISC8 Manuel utilisateur
PCI-ISC8
Intelligent 8 Channel
Serial Communications Controller
for PCI™ systems
REFERENCE MANUAL
769-00-001-4000
Version 1.0
November 1999
ALPHI TECHNOLOGY CORPORATION
6202 S. Maple Avenue #120
Tempe, AZ 85283 USA
PCI-ISC8 REFERENCE MANUAL
ALPHI TECHNOLOGY CORP. Page ii REV 1.0
Part Number : 724-20-000-4000 Copyright ALPHI Technology Corporation, 1999
Tel: (602) 838-2428
Fax: (602) 838-4477
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Part Number : 724-20-000-4000 Copyright ALPHI Technology Corporation, 1999
NOTICE
The information in this document has been carefully checked and is believed to be
entirely reliable. While all reasonable efforts to ensure accuracy have been taken in the
preparation of this manual, ALPHI TECHNOLOGY assumes no responsibility resulting
from omissions or errors in this manual, or from the use of information contain herein.
ALPHI TECHNOLOGY reserves the right to make any changes, without notice, to this or
any of ALPHI TECHNOLOGY’s products to improve reliability, performance, function or
design.
ALPHI TECHNOLOGY does not assume any liability arising out of the application or use
of any product or circuit described herein; nor does ALPHI TECHNOLOGY convey any
license under its patent rights or the rights of others.
ALPHI TECHNOLOGY CORPORATION
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted in advance.
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TABLE OF CONTENTS
1. GENERAL DESCRIPTION_______________________________________________1
1.1 INTRODUCTION__________________________________________________________1
1.2 FUNCTIONAL DESCRIPTION _______________________________________________1
1.3 REFERENCE MATERIALS LIST _____________________________________________3
2. HOST (PCI) SIDE______________________________________________________4
2.1 PCI CONFIGURATION REGISTERS __________________________________________4
2.2 PCI BASE ADDRESS REGISTERS ___________________________________________4
2.3 PCI OPERATION REGISTERS ______________________________________________4
3. C31 SIDE ____________________________________________________________5
3.1 INTERNAL ORGANIZATION ________________________________________________5
3.2 PCI INTERFACE__________________________________________________________5
3.3 DSP MEMORY AND REGISTER MAP SUMMARY________________________________7
3.4 RESET SIGNALS _________________________________________________________8
3.5 LOCAL DSP INTERRUPT SOURCES _________________________________________8
4. JUMPER DESCRIPTIONS_______________________________________________9
5. LED INDICATORS____________________________________________________10
6. CONNECTIONS______________________________________________________10
6.1 IP I/O CONNECTORS (P9, P10)_____________________________________________10
6.2 SERIAL RS232 PORT (P3) ________________________________________________11
6.3 EMULATOR CONNECTION (P4) ____________________________________________11
6.4 FACTORY USE (P2)______________________________________________________11
6.5 32 BIT PCI BUS (P1) _____________________________________________________11
7. STANDALONE OPERATION ___________________________________________11
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1. GENERAL DESCRIPTION
1.1 INTRODUCTION
The PCI-ISC8 is an intelligent DSP based serial communication board. This 3U board is
based on the PCI-IPC product and has been modified to remove the IP interface and to
support additional I/O features. The PCI-ISC8 provides mechanical support and the
electrical interfaces for an I/O mezzanine board. Multiple PCI-ISC8 boards may be installed
in a single system. The primary features of the PCI-ISC8 are as follows:
•Integrated DSP (TI TMS320C31) at 32 MHz to offload I/O operation from host or for
standalone applications
•Support for application specific serial mezzanine I/O
•Direct memory mapped control of DSP from PCI bus via AMCC 5933 PCI Chip
•Full interrupt support of host and DSP
•Front panel I/O connectors for all mezzanine I/O
•Four (4) 16 MHz Z85230 SCC devices
•All Z85230 I/O lines routed to mezzanine connectors
•One external interrupt input
1.2 FUNCTIONAL DESCRIPTION
A functional block diagram of the PCI-ISC8 is presented below in Figure 1-1. The jumper
placement and the connector placement is depicted in Figure 1-2. The PCI-ISC8 can
operate as a slave that is managed by the host processor on the PCI bus or it can operate
in a standalone mode of operation without a host.
The PCI-ISC8 is supported by ALPHI Technology under Windows NT by a Board Support
Package which is supplied with the card. Other documentation supplied with the card will
describe this support in full detail.
The card is also supported by a DSP Support Library providing the following features:
•Common access routines for communications with the HOST
•Mapping C language standard input and output by each of the DSPs to the onboard
8530 serial chips
•Identify the applicable card resources and parameters
All these are provided in a manner consistent across ALPHI Technology platforms. Other
documentation supplied with the card will describe the support in full detail.
A bootloader provided on the card allows for control by the HOST and for independent
operation in stand alone operation. User code can be downloaded to FLASH memory and
booted automatically on reset. Access to the card can be made both by the HOST PCI bus
and serially through the 8530.
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DSP C31
32 MHz
Local SRAM
128K x 32
Local FLASH
128K x 8 or
512K x 8
IP B
IP A
ConnectorConnector
CPCI
Bus
PCI to Local Bus
Bridge
Mailbox Registers
SCC8530
Serial Port
Figure 1.1: Block Diagram
P9
P1
P
4
W4
W2
W3 P
3P
2
P10
IP A
IP B
Figure 1.2: Jumper and Connector Locations
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1.3 REFERENCE MATERIALS LIST
The reader should refer to the PCI Local Bus Specification for a detailed explanation of the
PCI bus architecture and timing requirements. This specification is available from the
following source:
PCI Special Interest Group
PO Box 14070
Portland, OR 97214
Tel: (800) 433-5177
Tel: (503) 797-4207
Fax: (503) 234-6762
The reader is also referred to the S5933 PCI Controller data book:
AMCC Applied Micro Circuits Corporation
6195 Lusk Boulevard
San Diego, CA 92121-2793
Tel: (800) 755-2622
http://www.amcc.com
WindowsNT and Windows95 Programming Tools:
BlueWater Systems
144 Railroad Ave. Suite #217
Edmonds, WA 98020
Tel: (206) 771-3610
Fax: (206) 771-2742
E-Mail: [email protected]
Web: http://www.bluewatersystems.com
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2. HOST (PCI) SIDE
2.1 PCI CONFIGURATION REGISTERS
The card presents the following configuration values to the PCI system, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
Register Value (Meaning)
Vendor ID 0x13c5 (ALPHI Technology)
Device ID 0x0101 (PCI-ISC8) uses PCI-IPC ID
Revision ID 0x00
Class Code 0xff0000 (Device does not fit into defined class codes)
Interrupt Line 0xff
Interrupt Pin A
Multifunction Device No
Build In Self Test No
Latency Timer 0x00
Minimum Grant 0x00
Maximum Latency 0x00
Expansion ROM Size None
Table 2.1: PCI Configuration Registers
2.2 PCI BASE ADDRESS REGISTERS
The card requests base address regions from the PCI system after RESET, based on the
values stored in the NVRAM device read by the AMCC PCI interface chip.
The decode addresses of these regions are assigned by the host processor. The PCI-ISC8
uses 1 of the 5 AMCC mapped base address registers. The AMCC is normally programmed
at the factory to request the following resource from the PCI BIOS:
BASE
BAR From To Description Type
00x00000000 0x00000003F AMCC PCI Operation Registers MEM
Table 2.2: Base Address and Use
NOTE: The AMCC has been programmed to request memory above 1 Mbytes.
2.3 PCI OPERATION REGISTERS
The host processor communicates with the PCI-ISC8 card via the AMCC pass-through
interface. After the base address register has been programmed by the PCI configurator,
incoming PCI I/O or Memory cycles are used to access the registers of the AMCC chip. The
PCI Operation Registers of the AMCC 5933 chip are depicted below:
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Offset Register Name
0x00 OMB1 Outgoing Mailbox Register 1
0x04 OMB2 Outgoing Mailbox Register 2
0x08 OMB3 Outgoing Mailbox Register 3
0x0C OMB4 Outgoing Mailbox Register 4
0x10 IMB1 Incoming Mailbox Register 1
0x14 IMB2 Incoming Mailbox Register 2
0x18 IMB3 Incoming Mailbox Register 3
0x1C IMB4 Incoming Mailbox Register 4
0x20 FIFO Register Port (bi-directional)
0x24 MWAR Master Write Address Register
0x28 MWTC Master Write Transfer Counter
0x2C MRAR Master Read Address Register
0x30 MRTC Master Read Transfer Counter
0x34 MBEF Mailbox Empty/Full Status
0x38 INTCSR Interrupt Control/Status Register
0x3C MCSR Bus Master Control/Status Register
Table 2.3: AMCC Registers (HOST)
For more information about these registers refer to the AMCC PCI controller manual.
3. C31 SIDE
3.1 INTERNAL ORGANIZATION
The PCI-ISC8 card is divided into different sections. Each section and its relationship to
other sections will be discussed. The PCI-ISC8 sections are:
•PCI interface
•Local I/O interface
3.2 PCI INTERFACE
The local DSP processor communicates with the PCI bus through the AMCCS9533 chip
that provides bi-directional FIFO and Mailbox registers. The PCI-ISC8 can function as both
a servant (PCI target) or as a master (PCI initiator) for DMA access. The following interface
descriptions refer to the PCI interface as seen by the local DSP. The AMCC registers are
located at DSP address 0xf00080.
3.2.1 BI-DIRECTIONAL FIFO
Two separate FIFO data paths are implemented within the AMCCS9533, a read FIFO that
allows data transfers from the module to the PCI bus and a write FIFO that transfers data
from the PCI to the module. Size of the FIFO is 32 bit X 8. Read and write DMA access to
the host can occur via the FIFO registers if it is supported by the software on the HOST and
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is enabled. Alternatively, the FIFO registers can utilize a polled scheme on the HOST and
DSP. Both FIFOs are accessed via access to the same location as seen by the DSP, offset
0x08.
3.2.2 MAILBOX REGISTERS
The Mailbox registers of the AMCCS9533 provide a bi-directional data path that can be
used to send data or software control information between the HOST and DSP of that half
of the PCI-ISC8 module. Interrupts can be enabled based on a specific mailbox event.
There are 4 incoming mailboxes and 4 outgoing mailboxes. Each mailbox is 32 bits wide.
The address offsets for the mailboxes are shown below in Table 3-1.
3.2.3 ADDITIONAL REGISTERS
The AMCC S5933 PCI controller has a set of additional registers to control and monitor the
behavior of the PCI interface.
The address offsets of these registers are shown below in Table 3-1.
Offset Register Name
0x00 Incoming Mailbox Reg 1
0x01 Incoming Mailbox Reg 2
0x02 Incoming Mailbox Reg 3
0x03 Incoming Mailbox Reg 4
0x04 Outgoing Mailbox Reg 1
0x05 Outgoing Mailbox Reg 2
0x06 Outgoing Mailbox Reg 3
0x07 Outgoing Mailbox Reg 4
0x08 Add-on FIFO port
0x09 Bus master write Address Register
0x0A Add-on Pass through Address
0x0B Add-on Pass trough Data
0x0C Bus master read Address Register
0x0D Add-on Mailbox Empty/full Status
0x0E Add-on Interrupt Control
0x0F Add-on General Control/Status Register
Table 3.1: AMCC Registers (DSP)
For more information about these registers refer to the AMCC PCI controller manual.
Table des matières
